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Achieving Non-Inclusive Cache Performance with Inclusive Caches: Temporal Locality Aware (TLA) Cache Management Policies
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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Design and implementation of the blue gene/P snoop filter
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On the inclusion properties for multi-level cache hierarchies
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An evaluation of directory schemes for cache coherence
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Tradeoffs in two-level on-chip caching
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Piranha: a scalable architecture based on single-chip multiprocessing
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Performance evaluation of exclusive cache hierarchies
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The on-chip 3-MB subarray-based third-level cache on an Itanium microprocessor
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Pinpointing Representative Portions of Large Intel® Itanium® Programs with Dynamic Instrumentation
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Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches
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Cache replacement with dynamic exclusion
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Adaptive insertion policies for managing shared caches
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High performance cache replacement using re-reference interval prediction (RRIP)
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On the inclusion properties for multi-level cache hierarchies
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An evaluation of directory schemes for cache coherence
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Improving direct-mapped cache performance by the addition of a small fully-associative cache prefetch buffers
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What points at this work
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