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A Case for a Flexible Scalar Unit in SIMT Architecture

https://doi.org/10.1109/ipdps.2014.21

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-3-540-24644-2_35openalex-snapshot

Cetus – An Extensible Compiler Infrastructure for Source-to-Source Transformation

inferredcites →https://doi.org/10.1007/978-3-642-14122-5_8openalex-snapshot

Dynamic Detection of Uniform and Affine Vectors in GPGPU Computations

inferredcites →https://doi.org/10.1109/2.485896openalex-snapshot

Spert-II: a vector microprocessor system

inferredcites →https://doi.org/10.1109/cgo.2013.6494995openalex-snapshot

Convergence and scalarization for data-parallel architectures

inferredcites →https://doi.org/10.1109/hpca.1996.501193openalex-snapshot

Decoupled vector architectures

inferredcites →https://doi.org/10.1109/hpca.2011.5749714openalex-snapshot

Thread block compaction for efficient SIMT control flow

inferredcites →https://doi.org/10.1109/hpca.2012.6168948openalex-snapshot

CPU-assisted GPGPU on fused CPU-GPU architectures

inferredcites →https://doi.org/10.1109/hpca.2014.6835939openalex-snapshot

Warp-level divergence in GPUs: Characterization, impact, and mitigation

inferredcites →https://doi.org/10.1109/iiswc.2009.5306797openalex-snapshot

Rodinia: A benchmark suite for heterogeneous computing

inferredcites →https://doi.org/10.1109/isca.2001.937427openalex-snapshot

Speculative precomputation: long-range prefetching of delinquent loads

inferredcites →https://doi.org/10.1109/isca.2002.1003576openalex-snapshot

Using a user-level memory thread for correlation prefetching

inferredcites →https://doi.org/10.1109/isca.2002.1003586openalex-snapshot

Tarantula: a vector extension to the alpha architecture

inferredcites →https://doi.org/10.1109/isca.2004.1310763openalex-snapshot

The vector-thread architecture

inferredcites →https://doi.org/10.1109/ispass.2009.4919648openalex-snapshot

Analyzing CUDA workloads using a detailed GPU simulator

inferredcites →https://doi.org/10.1109/micro.1997.645807openalex-snapshot

Out-of-order vector architectures

inferredcites →https://doi.org/10.1109/micro.2002.1176257openalex-snapshot

Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks

inferredcites →https://doi.org/10.1109/micro.2007.12openalex-snapshot

Microarchitectural Design Space Exploration Using an Architecture-Centric Approach

inferredcites →https://doi.org/10.1109/micro.2007.30openalex-snapshot

Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow

inferredcites →https://doi.org/10.1109/micro.2010.44openalex-snapshot

Many-Thread Aware Prefetching Mechanisms for GPGPU Applications

inferredcites →https://doi.org/10.1109/sc.2008.5213922openalex-snapshot

High performance discrete Fourier transforms on graphics processors

inferredcites →https://doi.org/10.1145/1028176.1006736openalex-snapshot

The Vector-Thread Architecture

inferredcites →https://doi.org/10.1145/1669112.1669172openalex-snapshot

McPAT

inferredcites →https://doi.org/10.1145/1735970.1736054openalex-snapshot

COMPASS

inferredcites →https://doi.org/10.1145/1736020.1736054openalex-snapshot

COMPASS

inferredcites →https://doi.org/10.1145/1810085.1810104openalex-snapshot

Streamlining GPU applications on the fly

inferredcites →https://doi.org/10.1145/1815961.1815992openalex-snapshot

Dynamic warp subdivision for integrated branch and memory divergence tolerance

inferredcites →https://doi.org/10.1145/1941553.1941590openalex-snapshot

Accelerating CUDA graph algorithms at maximum warp

inferredcites →https://doi.org/10.1145/2000064.2000080openalex-snapshot

Exploring the tradeoffs between programmability and efficiency in data-parallel accelerators

inferredcites →https://doi.org/10.1145/2451116.2451158openalex-snapshot

OWL

inferredcites →https://doi.org/10.1145/2485922.2485951openalex-snapshot

Orchestrated scheduling and prefetching for GPGPUs

inferredcites →https://doi.org/10.1145/2485922.2485953openalex-snapshot

Maximizing SIMD resource utilization in GPGPUs with SIMD lane permutation

inferredcites →https://doi.org/10.1145/339647.339693openalex-snapshot

Vector instruction set support for conditional operations

inferredcites →https://doi.org/10.1145/379240.379248openalex-snapshot

Speculative precomputation

inferredcites →https://doi.org/10.1145/379240.379249openalex-snapshot

Dynamically allocating processor resources between nearby and distant ILP

inferredcites →https://doi.org/10.1145/379240.379250openalex-snapshot

Tolerating memory latency through software-controlled pre-execution in simultaneous multithreading processors

inferredcites →https://doi.org/10.1145/384285.379250openalex-snapshot

Tolerating memory latency through software-controlled pre-execution in simultaneous multithreading processors

inferredcites →https://doi.org/10.1145/545214.545235openalex-snapshot

Using a user-level memory thread for correlation prefetching

inferredcites →https://doi.org/10.1145/545214.545247openalex-snapshot

Tarantula

inferredcites →https://doi.org/10.1145/605397.605415openalex-snapshot

Design and evaluation of compiler algorithms for pre-execution

inferredcites →https://doi.org/10.1145/635508.605415openalex-snapshot

Design and evaluation of compiler algorithms for pre-execution

inferredcites →https://doi.org/10.1145/859618.859664openalex-snapshot

Overcoming the limitations of conventional vector processors

inferredcites →https://doi.org/10.5555/1413370.1413373openalex-snapshot

High performance discrete Fourier transforms on graphics processors

inferredcites →https://doi.org/10.5555/266800.266816openalex-snapshot

Out-of-order vector architectures

inferredcites →https://doi.org/10.5555/774861.774892openalex-snapshot

Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-031-01759-9openalex-snapshot

General-Purpose Graphics Processor Architectures

inferred← citeshttps://doi.org/10.1016/j.jpdc.2018.11.012openalex-snapshot

A survey of architectural approaches for improving GPGPU performance, programmability and heterogeneity

inferred← citeshttps://doi.org/10.1016/j.micpro.2020.103176openalex-snapshot

EREER: Energy-aware register file and execution unit using exploiting redundancy in GPGPUs

inferred← citeshttps://doi.org/10.1109/hpca.2017.51openalex-snapshot

G-Scalar: Cost-Effective Generalized Scalar Execution Architecture for Power-Efficient GPUs

inferred← citeshttps://doi.org/10.1109/hpca.2018.00041openalex-snapshot

WIR: Warp Instruction Reuse to Minimize Repeated Computations in GPUs

inferred← citeshttps://doi.org/10.1109/ia351965.2020.00010openalex-snapshot

Supporting Irregularity in Throughput-Oriented Computing by SIMT-SIMD Integration

inferred← citeshttps://doi.org/10.1109/icppw.2016.23openalex-snapshot

Energy Efficient Affine Register File for GPU Microarchitecture

inferred← citeshttps://doi.org/10.1109/ipdps.2016.74openalex-snapshot

Balancing Scalar and Vector Execution on GPU Architectures

inferred← citeshttps://doi.org/10.1109/micro50266.2020.00065openalex-snapshot

Duplo: Lifting Redundant Memory Accesses of Deep Neural Networks for GPU Tensor Cores

inferred← citeshttps://doi.org/10.1109/tc.2016.2619348openalex-snapshot

Improving Energy Efficiency of GPUs through Data Compression and Compressed Execution

inferred← citeshttps://doi.org/10.1109/tcc.2024.3511548openalex-snapshot

Efficient Dynamic Resource Management for Spatial Multitasking GPUs

inferred← citeshttps://doi.org/10.1109/tvlsi.2018.2817564openalex-snapshot

SiMT-DSP: A Massively Multithreaded DSP Architecture

inferred← citeshttps://doi.org/10.1145/2749469.2750417openalex-snapshot

Warped-compression

inferred← citeshttps://doi.org/10.1145/2872887.2750417openalex-snapshot

Warped-compression

inferred← citeshttps://doi.org/10.1145/3079856.3080205openalex-snapshot

Decoupled Affine Computation for SIMT GPUs

inferred← citeshttps://doi.org/10.1145/3133218openalex-snapshot

Architecture and Compiler Support for GPUs Using Energy-Efficient Affine Register Files

inferred← citeshttps://doi.org/10.1145/3140659.3080205openalex-snapshot

Decoupled Affine Computation for SIMT GPUs

inferred← citeshttps://doi.org/10.1145/3373376.3378520openalex-snapshot

Dimensionality-Aware Redundant SIMT Instruction Elimination

inferred← citeshttps://doi.org/10.1145/3579371.3589039openalex-snapshot

R2D2: Removing ReDunDancy Utilizing Linearity of Address Generation in GPUs

inferred← citeshttps://doi.org/10.1145/3712285.3759830openalex-snapshot

RedSan: A Redundant Memory Instruction Sanitizer for GPU Programs

inferred← citeshttps://doi.org/10.17760/d20251481openalex-snapshot

Scalar-vector GPU architectures

inferred← citeshttps://doi.org/10.2200/s00848ed1v01y201804cac044openalex-snapshot

General-Purpose Graphics Processor Architectures

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