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Microarchitectural Design Space Exploration Using an Architecture-Centric Approach
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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An Approach to Performance Prediction for Parallel Applications
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HLSpower: Hybrid Statistical Modeling of the Superscalar Power-Performance Design Space
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Neural networks for pattern recognition
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'The Concise Oxford dictionary.'
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Microarchitecture Sensitive Empirical Models for Compiler Optimizations
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Efficient Design Space Exploration of High Performance Embedded Out-of-Order Processors
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Construction and Use of Linear Regression Models for Processor Performance Analysis
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Liquid SIMD: Abstracting SIMD Hardware using Lightweight Dynamic Mapping
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Illustrative Design Space Studies with Microarchitectural Regression Models
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Towards Efficient Supercomputing: A Quest for the Right Metric
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HLS: combining statistical and symbolic simulation to guide microprocessor designs
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Wattch: a framework for architectural-level power analysis and optimizations
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SMARTS: accelerating microarchitecture simulation via rigorous statistical sampling
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A first-order superscalar processor model
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Control flow modeling in statistical simulation for accurate and efficient processor design studies
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SE2 when processors hit the power wall (or "when the CPU hits the fan")
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Introducing Control Flow into Vectorized Code
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Using PredictiveModeling for Cross-Program Design Space Exploration in Multicore Systems
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ClawHMMER: A Streaming HMMer-Search Implementatio
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A processor architecture for Horizon
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Performance prediction based on inherent program similarity
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Accurate and efficient regression modeling for microarchitectural performance and power prediction
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Efficiently exploring architectural design spaces via predictive modeling
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Automatic performance model construction for the fast software exploration of new hardware designs
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Sparse matrix solvers on the GPU
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Ray tracing on programmable graphics hardware
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Methods of inference and learning for performance modeling of parallel applications
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Theoretical modeling of superscalar processor performance
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The SimpleScalar tool set, version 2.0
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Computer display of curved surfaces
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Efficient performance prediction for modern microprocessors
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Texture and reflection in computer generated images
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Conversion of control dependence to data dependence
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Automatically characterizing large scale program behavior
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Chap - a SIMD graphics processor
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Sparse matrix solvers on the GPU
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Chap - a SIMD graphics processor
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Efficient control flow restructuring for GPUs
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FastLanes: An FPGA accelerated GPU microarchitecture simulator
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Dynamic front-end sharing in graphics processing units
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Comparative Analysis of Processors Performance Using ANN
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Machine Learning Models to Predict Performance of Computer System Design Alternatives
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Thread Similarity Matrix: Visualizing Branch Divergence in GPGPU Programs
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Dynamic SIMD re-convergence with paired-path comparison
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ArchExplorer.org: A methodology for facilitating a fair Comparison of research ideas
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Mechanistic-empirical processor performance modeling for constructing CPI stacks on real hardware
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Stargazer: Automated regression-based GPU design space exploration
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A mechanistic performance model for superscalar in-order processors
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Characterizing and evaluating a key-value store application on heterogeneous CPU-GPU systems
inferred← citeshttps://doi.org/10.1109/ispass.2015.7095804openalex-snapshot
DRAW: investigating benefits of adaptive fetch group size on GPU
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EmerGPU: Understanding and mitigating resonance-induced voltage noise in GPU architectures
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Fast IPC estimation for performance projections using proxy suites and decision trees
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Full-System Simulation of Mobile CPU/GPU Platforms
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Horus: A Modular GPU Emulator Framework
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MeMo: Enhancing Representative Sampling via Mechanistic Micro-Model Signatures
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Execution Units Power-Gating to Improve Energy Efficiency of GPGPUs
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ScaleGPU: GPU Architecture for Memory-Unaware GPU Programming
inferred← citeshttps://doi.org/10.1109/micro.2008.4771788openalex-snapshot
Tradeoffs in designing accelerator architectures for visual computing
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CPR: Composable performance regression for scalable multiprocessor models
inferred← citeshttps://doi.org/10.1109/micro.2010.45openalex-snapshot
Improving SIMT Efficiency of Global Rendering Algorithms with Architectural Support for Dynamic Micro-Kernels
inferred← citeshttps://doi.org/10.1109/micro.2010.50openalex-snapshot
Throughput-Effective On-Chip Networks for Manycore Accelerators
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Cache-Conscious Wavefront Scheduling
inferred← citeshttps://doi.org/10.1109/micro.2014.24openalex-snapshot
Accelerating Irregular Algorithms on GPGPUs Using Fine-Grain Hardware Worklists
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FineReg: Fine-Grained Register File Management for Augmenting GPU Throughput
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SAVE: Sparsity-Aware Vector Engine for Accelerating DNN Training and Inference on CPUs
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Kilo TM: Hardware Transactional Memory for GPU Architectures
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TCU: Thread compaction unit for GPGPU applications on mobile graphics hardware
inferred← citeshttps://doi.org/10.1109/nas.2013.35openalex-snapshot
An Optimized GP-GPU Warp Scheduling Algorithm for Sparse Matrix-Vector Multiplication
inferred← citeshttps://doi.org/10.1109/pacrim.2009.5291239openalex-snapshot
Architecting graphics processors for non-graphics compute acceleration
inferred← citeshttps://doi.org/10.1109/pact.2011.16openalex-snapshot
PEPSC: A Power-Efficient Processor for Scientific Computing
inferred← citeshttps://doi.org/10.1109/pact.2011.62openalex-snapshot
Correctly Treating Synchronizations in Compiling Fine-Grained SPMD-Threaded Programs for CPU
inferred← citeshttps://doi.org/10.1109/pact.2011.63openalex-snapshot
Divergence Analysis and Optimizations
inferred← citeshttps://doi.org/10.1109/pact.2015.38openalex-snapshot
Exploiting Inter-Warp Heterogeneity to Improve GPGPU Performance
inferred← citeshttps://doi.org/10.1109/pact.2019.00034openalex-snapshot
EDGE: Event-Driven GPU Execution
inferred← citeshttps://doi.org/10.1109/pccc.2016.7820638openalex-snapshot
A reuse distance based performance analysis on GPU L1 data cache
inferred← citeshttps://doi.org/10.1109/pdp.2012.62openalex-snapshot
SIMT Microscheduling: Reducing Thread Stalling in Divergent Iterative Algorithms
inferred← citeshttps://doi.org/10.1109/pdp.2016.79openalex-snapshot
Towards Architectural Design Space Exploration for Heterogeneous Manycores
inferred← citeshttps://doi.org/10.1109/pesgm.2014.6939325openalex-snapshot
A fine-grained parallel EMTP algorithm compatible to graphic processing units
inferred← citeshttps://doi.org/10.1109/samos.2011.6045443openalex-snapshot
Smart cache: A self adaptive cache architecture for energy efficiency
inferred← citeshttps://doi.org/10.1109/samos.2012.6404177openalex-snapshot
Efficient system design using the Statistical Analysis of Architectural Bottlenecks methodology
inferred← citeshttps://doi.org/10.1109/samos.2016.7818338openalex-snapshot
Genesys: Automatically generating representative training sets for predictive benchmarking
inferred← citeshttps://doi.org/10.1109/sbac-pad.2010.38openalex-snapshot
Performance Debugging of GPGPU Applications with the Divergence Map
inferred← citeshttps://doi.org/10.1109/sbac-pad.2012.22openalex-snapshot
Divergence Analysis with Affine Constraints
inferred← citeshttps://doi.org/10.1109/sc41406.2024.00072openalex-snapshot
Learning Generalizable Program and Architecture Representations for Performance Modeling
inferred← citeshttps://doi.org/10.1109/scw63240.2024.00186openalex-snapshot
AI-Assisted Design-Space Analysis of High-Performance Arm Processors
inferred← citeshttps://doi.org/10.1109/sips.2009.5336269openalex-snapshot
Development and evaluation of scalable video motion estimators on GPU
inferred← citeshttps://doi.org/10.1109/tc.2010.280openalex-snapshot
An Empirical Architecture-Centric Approach to Microarchitectural Design Space Exploration
inferred← citeshttps://doi.org/10.1109/tc.2012.144openalex-snapshot
A Customized Processor for Energy Efficient Scientific Computing
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CRAT: Enabling Coordinated Register Allocation and Thread-Level Parallelism Optimization for GPUs
inferred← citeshttps://doi.org/10.1109/tc.2019.2906869openalex-snapshot
CD-Xbar: A Converge-Diverge Crossbar Network for High-Performance GPUs
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MIPSGPU: Minimizing Pipeline Stalls for GPUs With Non-Blocking Execution
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Accelerating Architectural Simulation Via Statistical Techniques: A Survey
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An Accurate GPU Performance Model for Effective Control Flow Divergence Optimization
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QIG: Quantifying the Importance and Interaction of GPGPU Architecture Parameters
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Optimizing Cache Bypassing and Warp Scheduling for GPUs
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A Reconfigurable SIMT Processor for Mobile Ray Tracing With Contention Reduction in Shared Memory
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An implementation of a SIMT architecture-based stream processor
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SPRING: A Sparsity-Aware Reduced-Precision Monolithic 3D CNN Accelerator Architecture for Training and Inference
inferred← citeshttps://doi.org/10.1109/tpds.2014.2313342openalex-snapshot
Efficient GPU Spatial-Temporal Multitasking
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Dynamic Resizing on Active Warps Scheduler to Hide Operation Stalls on GPUs
inferred← citeshttps://doi.org/10.1109/tpds.2017.2773516openalex-snapshot
IBOM: An Integrated and Balanced On-Chip Memory for High Performance GPGPUs
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Exploring Customizable Heterogeneous Power Distribution and Management for Datacenter
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Locality Protected Dynamic Cache Allocation Scheme on GPUs
inferred← citeshttps://doi.org/10.1109/tsp.2015.7296320openalex-snapshot
A design of a GP-GPU based stream processor for an image processing
inferred← citeshttps://doi.org/10.1109/tvlsi.2023.3311620openalex-snapshot
Microarchitecture Design Space Exploration via Pareto-Driven Active Learning
inferred← citeshttps://doi.org/10.1109/tvlsi.2024.3368075openalex-snapshot
BSSE: Design Space Exploration on the BOOM With Semi-Supervised Learning
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Many-Thread Aware Compression in GPGPUs
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AI for Code: Reinforcement-Learned Compiler Optimizations for HPC Workflows
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A mechanistic performance model for superscalar out-of-order processors
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How GPUs can outperform ASICs for fast LDPC decoding
inferred← citeshttps://doi.org/10.1145/1572769.1572797openalex-snapshot
Stream compaction for deferred shading
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Increasing memory miss tolerance for SIMD cores
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Using the graphics processor unit to realize data streaming operations
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