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Architecture and Compiler Support for GPUs Using Energy-Efficient Affine Register Files

https://doi.org/10.1145/3133218
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-3-642-14122-5_8openalex-snapshot
Dynamic Detection of Uniform and Affine Vectors in GPGPU Computations
inferredcites →https://doi.org/10.1007/978-3-642-32820-6_85openalex-snapshot
OpenACC — First Experiences with Real-World Applications
inferredcites →https://doi.org/10.1109/4.509850openalex-snapshot
CACTI: an enhanced cache access and cycle time model
inferredcites →https://doi.org/10.1109/cgo.2004.1281665openalex-snapshot
LLVM: a compilation framework for lifelong program analysis & transformation
inferredcites →https://doi.org/10.1109/cgo.2013.6494995openalex-snapshot
Convergence and scalarization for data-parallel architectures
inferredcites →https://doi.org/10.1109/cgo20717.2013openalex-snapshot
Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization (CGO)
inferredcites →https://doi.org/10.1109/hotchips.2013.7478286openalex-snapshot
Heterogeneous system architecture overview
inferredcites →https://doi.org/10.1109/hpca.2013.6522330openalex-snapshot
Power-efficient computing for compute-intensive GPGPU applications
inferredcites →https://doi.org/10.1109/hpca.2013.6522337openalex-snapshot
Warped register file: A power efficient register file for GPGPUs
inferredcites →https://doi.org/10.1109/iiswc.2009.5306797openalex-snapshot
Rodinia: A benchmark suite for heterogeneous computing
inferredcites →https://doi.org/10.1109/ipdps.2014.21openalex-snapshot
A Case for a Flexible Scalar Unit in SIMT Architecture
inferredcites →https://doi.org/10.1109/ipdps.2014.22openalex-snapshot
Scalar Waving: Improving the Efficiency of SIMD Execution on GPUs
inferredcites →https://doi.org/10.1109/ispass.2009.4919648openalex-snapshot
Analyzing CUDA workloads using a detailed GPU simulator
inferredcites →https://doi.org/10.1109/ispass.2013.6557173openalex-snapshot
Characterizing scalar opportunities in GPGPU applications
inferredcites →https://doi.org/10.1109/mcse.2010.69openalex-snapshot
OpenCL: A Parallel Programming Standard for Heterogeneous Computing Systems
inferredcites →https://doi.org/10.1145/1365490.1365500openalex-snapshot
Scalable Parallel Programming with CUDA
inferredcites →https://doi.org/10.1145/1815961.1815998openalex-snapshot
An integrated GPU power and performance model
inferredcites →https://doi.org/10.1145/2000064.2000093openalex-snapshot
Energy-efficient mechanisms for managing thread context in throughput processors
inferredcites →https://doi.org/10.1145/2000064.2000094openalex-snapshot
SRAM-DRAM hybrid memory with applications to efficient register files in fine-grained multi-threading
inferredcites →https://doi.org/10.1145/2155620.2155675openalex-snapshot
A compile-time managed multi-level register file hierarchy
inferredcites →https://doi.org/10.1145/2464996.2465022openalex-snapshot
Exploiting uniform vector instructions for GPGPU performance, energy efficiency, and opportunistic reliability enhancement
inferredcites →https://doi.org/10.1145/2485922.2485934openalex-snapshot
Microarchitectural mechanisms to exploit value structure in SIMT architectures
inferredcites →https://doi.org/10.1145/2485922.2485952openalex-snapshot
An energy-efficient and scalable eDRAM-based register file architecture for GPGPU
inferredcites →https://doi.org/10.1145/2485922.2485964openalex-snapshot
GPUWattch
inferredcites →https://doi.org/10.1145/2523815openalex-snapshot
Divergence analysis
inferredcites →https://doi.org/10.1145/2611758openalex-snapshot
Power Modeling for GPU Architectures Using McPAT
inferredcites →https://doi.org/10.1145/2744769.2744785openalex-snapshot
A STT-RAM-based low-power hybrid register file for GPGPUs
inferredcites →https://doi.org/10.1145/2827697openalex-snapshot
Exploring Soft-Error Robust and Energy-Efficient Register File in GPGPUs using Resistive Memory
inferredcites →https://doi.org/10.1145/88616.88621openalex-snapshot
The priority-based coloring approach to register allocation

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1016/j.sysarc.2020.101712openalex-snapshot
A framework for scheduling dependent programs on GPU architectures
inferred← citeshttps://doi.org/10.1016/j.sysarc.2020.101783openalex-snapshot
Experiment and enabled flow for GPGPU-Sim simulators with fixed-point instructions
inferred← citeshttps://doi.org/10.1080/09540091.2023.2272586openalex-snapshot
Accelerating AI performance with the incorporation of TVM and MediaTek NeuroPilot
inferred← citeshttps://doi.org/10.1109/access.2024.3397195openalex-snapshot
Case Study: Optimization Methods With TVM Hybrid-OP on RISC-V Packed SIMD
inferred← citeshttps://doi.org/10.1109/cgo57630.2024.10444795openalex-snapshot
Energy-Aware Tile Size Selection for Affine Programs on GPUs
inferred← citeshttps://doi.org/10.1109/tpds.2019.2944602openalex-snapshot
cCUDA: Effective Co-Scheduling of Concurrent Kernels on GPUs
inferred← citeshttps://doi.org/10.1109/tvlsi.2025.3574427openalex-snapshot
RISC-V-Based GPGPU With Vector Capabilities for High-Performance Computing
inferred← citeshttps://doi.org/10.1145/3204919.3207894openalex-snapshot
ViennaCL++
inferred← citeshttps://doi.org/10.1145/3229710.3229722openalex-snapshot
Enable the Flow for GPGPU-Sim Simulators with Fixed-Point Instructions
inferred← citeshttps://doi.org/10.1145/3229710.3229723openalex-snapshot
Scheduling Methods to Optimize Dependent Programs for GPU Architecture
inferred← citeshttps://doi.org/10.1145/3339186.3339193openalex-snapshot
Devise Rust Compiler Optimizations on RISC-V Architectures with SIMD Instructions
inferred← citeshttps://doi.org/10.1145/3470644openalex-snapshot
Pointer-Based Divergence Analysis for OpenCL 2.0 Programs
inferred← citeshttps://doi.org/10.1145/3547276.3548518openalex-snapshot
Efficient Support of the Scan Vector Model for RISC-V Vector Extension
inferred← citeshttps://doi.org/10.1145/3569939openalex-snapshot
Auto-tuning Fixed-point Precision with TVM on RISC-V Packed SIMD Extension
inferred← citeshttps://doi.org/10.1145/3677333.3678148openalex-snapshot
The Rewriting of DataRaceBench Benchmark for OpenCL Program Validations
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