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Performance and Energy Analysis of the Restricted Transactional Memory Implementation on Haswell
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/hpca.2007.346189openalex-snapshot
A Scalable, Non-blocking Approach to Transactional Memory
inferredcites →https://doi.org/10.1109/hpca.2007.346204openalex-snapshot
LogTM-SE: Decoupling Hardware Transactional Memory from Caches
inferredcites →https://doi.org/10.1109/iiswc.2008.4636089openalex-snapshot
STAMP: Stanford Transactional Applications for Multi-Processing
inferredcites →https://doi.org/10.1109/iiswc.2010.5648812openalex-snapshot
Eigenbench: A simple exploration tool for orthogonal TM characteristics
inferredcites →https://doi.org/10.1109/isca.1993.698569openalex-snapshot
Transactional Memory: Architectural Support For Lock-free Data Structures
inferredcites →https://doi.org/10.1109/isca.2004.1310767openalex-snapshot
Transactional memory coherence and consistency
inferredcites →https://doi.org/10.1109/micro.2010.23openalex-snapshot
A Dynamically Adaptable Hardware Transactional Memory
inferredcites →https://doi.org/10.1109/micro.2012.12openalex-snapshot
Transactional Memory Architecture and Implementation for IBM System Z
inferredcites →https://doi.org/10.1109/sbac-pad.2010.11openalex-snapshot
Characterizing Energy Consumption in Hardware Transactional Memory Systems
inferredcites →https://doi.org/10.1109/tpds.2010.49openalex-snapshot
Time-Based Software Transactional Memory
inferredcites →https://doi.org/10.1145/1028176.1006711openalex-snapshot
Transactional Memory Coherence and Consistency
inferredcites →https://doi.org/10.1145/1508244.1508263openalex-snapshot
Early experience with a commercial hardware transactional memory implementation
inferredcites →https://doi.org/10.1145/1508284.1508263openalex-snapshot
Early experience with a commercial hardware transactional memory implementation
inferredcites →https://doi.org/10.1145/2370816.2370836openalex-snapshot
Evaluation of Blue Gene/Q hardware support for transactional memories
inferredcites →https://doi.org/10.1145/2500727.2500745openalex-snapshot
Opportunities and pitfalls of multi-core scaling using hardware transaction memory
inferredcites →https://doi.org/10.1145/2503210.2503232openalex-snapshot
Performance evaluation of Intel® transactional synchronization extensions for high-performance computing
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-319-09873-9_40openalex-snapshot
Automatic Tuning of the Parallelism Degree in Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1007/s00446-019-00363-1openalex-snapshot
Extending hardware transactional memory capacity via rollback-only transactions and suspend/resume
inferred← citeshttps://doi.org/10.1007/s11227-016-1944-zopenalex-snapshot
Leveraging irrevocability to deal with signature saturation in hardware transactional memory
inferred← citeshttps://doi.org/10.1007/s11227-017-2188-2openalex-snapshot
Privatizing transactions for Lee’s algorithm in commercial hardware transactional memory
inferred← citeshttps://doi.org/10.1007/s11227-019-02844-3openalex-snapshot
How good is the OpenPOWER architecture for high-performance CPU-oriented weather forecasting applications?
inferred← citeshttps://doi.org/10.1016/j.jpdc.2017.01.002openalex-snapshot
Enhancing scalability in best-effort hardware transactional memory systems
inferred← citeshttps://doi.org/10.1016/j.jpdc.2018.12.007openalex-snapshot
Analyzing and optimizing the performance and energy efficiency of transactional scientific applications on large-scale NUMA systems with HTM support
inferred← citeshttps://doi.org/10.1016/j.jpdc.2019.04.018openalex-snapshot
Improving hardware transactional memory parallelization of computational geometry algorithms using privatizing transactions
inferred← citeshttps://doi.org/10.1016/j.jpdc.2020.06.009openalex-snapshot
PfTouch: Concurrent page-fault handling for Intel restricted transactional memory
inferred← citeshttps://doi.org/10.1109/iisec56263.2022.9998279openalex-snapshot
A Performance Improvement Model for Market Surveillance Application
inferred← citeshttps://doi.org/10.1109/iiswc.2014.6983060openalex-snapshot
Thread-level speculation on off-the-shelf hardware transactional memory
inferred← citeshttps://doi.org/10.1109/ipdps.2018.00090openalex-snapshot
Quantifying the Performance and Energy-Efficiency Impact of Hardware Transactional Memory on Scientific Applications on Large-Scale NUMA Systems
inferred← citeshttps://doi.org/10.1109/ipdps57955.2024.00081openalex-snapshot
LockillerTM: Enhancing Performance Lower Bounds in Best-Effort Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1109/mascots.2017.29openalex-snapshot
An Analytical Model of Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00067openalex-snapshot
Chaining Transactions for Effective Concurrency Management in Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1109/sbac-pad.2014.41openalex-snapshot
Improving Signature Behavior by Irrevocability in Transactional Memory Systems
inferred← citeshttps://doi.org/10.1109/tpds.2018.2861712openalex-snapshot
The Case for Phase-Based Transactional Memory
inferred← citeshttps://doi.org/10.1109/tpds.2019.2963030openalex-snapshot
Concurrent Irrevocability in Best-Effort Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1109/tpds.2021.3085210openalex-snapshot
DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memory
inferred← citeshttps://doi.org/10.1109/tpds.2022.3206777openalex-snapshot
LosaTM: A Hardware Transactional Memory Integrated With a Low-Overhead Scenario-Awareness Conflict Manager
inferred← citeshttps://doi.org/10.1109/uic-atc.2017.8397653openalex-snapshot
DAdHTM: Low overhead dynamically adaptive hardware transactional memory for large graphs a scalability study
inferred← citeshttps://doi.org/10.1145/3079079.3079094openalex-snapshot
Revisiting phased transactional memory
inferred← citeshttps://doi.org/10.1145/3196494.3196508openalex-snapshot
Automated Detection, Exploitation, and Elimination of Double-Fetch Bugs using Modern CPU Features
inferred← citeshttps://doi.org/10.1145/3293883.3295714openalex-snapshot
Stretching the capacity of hardware transactional memory in IBM POWER architectures
inferred← citeshttps://doi.org/10.1145/3459898.3463901openalex-snapshot
Understanding and utilizing hardware transactional memory capacity
inferred← citeshttps://doi.org/10.1145/3497776.3517778openalex-snapshot
Cape: compiler-aided program transformation for HTM-based cache side-channel defense
inferred← citeshttps://doi.org/10.47749/t/unicamp.2015.949473openalex-snapshot
Scheduling and serialization techniques for transactional memories
inferred← citeshttps://doi.org/10.47749/t/unicamp.2020.1149098openalex-snapshot
Improving hardware/software transactional memory codesign
inferred← citeshttps://doi.org/10.5753/wscad.2015.14285openalex-snapshot
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