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Transactional Memory Architecture and Implementation for IBM System Z
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/hotchips.2012.7476505openalex-snapshot
IBM zNext - the 3rd generation high frequency microprocessor chip
inferredcites →https://doi.org/10.1109/hpca.2006.1598134openalex-snapshot
LogTM: Log-based Transactional Memory
inferredcites →https://doi.org/10.1109/isca.1993.698569openalex-snapshot
Transactional Memory: Architectural Support For Lock-free Data Structures
inferredcites →https://doi.org/10.1109/isca.2004.1310767openalex-snapshot
Transactional memory coherence and consistency
inferredcites →https://doi.org/10.1109/isca.2006.9openalex-snapshot
Architectural Semantics for Practical Transactional Memory
inferredcites →https://doi.org/10.1109/mm.2009.34openalex-snapshot
Rock: A High-Performance Sparc CMT Processor
inferredcites →https://doi.org/10.1145/1168857.1168903openalex-snapshot
Tradeoffs in transactional memory virtualization
inferredcites →https://doi.org/10.1145/1250662.1250684openalex-snapshot
Hardware atomicity for reliable software speculation
inferredcites →https://doi.org/10.1145/1345206.1345233openalex-snapshot
On the correctness of transactional memory
inferredcites →https://doi.org/10.1145/161468.161469openalex-snapshot
A methodology for implementing highly concurrent data objects
inferredcites →https://doi.org/10.1147/jrd.2009.5388579openalex-snapshot
IBM System z10 processor cache subsystem microarchitecture
inferredcites →https://doi.org/10.1147/jrd.2011.2173962openalex-snapshot
IBM zEnterprise 196 microprocessor and cache subsystem
inferredcites →https://doi.org/10.5555/563998.564036openalex-snapshot
Speculative lock elision: enabling highly concurrent multithreaded execution
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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PleaseTM: Enabling transaction conflict management in requester-wins hardware transactional memory
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Safety Hints for HTM Capacity Abort Mitigation
inferred← citeshttps://doi.org/10.1109/hpca68181.2026.11408623openalex-snapshot
Enterprise Class On-Chip Accelerator Integration
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Easy Lock-Free Indexing in Non-Volatile Memory
inferred← citeshttps://doi.org/10.1109/icpp.2015.64openalex-snapshot
Green-CM: Energy Efficient Contention Management for Transactional Memory
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Do C and Java programs scale differently on Hardware Transactional Memory?
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Transaction-Based Core Reliability
inferred← citeshttps://doi.org/10.1109/jssc.2025.3621731openalex-snapshot
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Unbounded Hardware Transactional Memory for a Hybrid DRAM/NVM Memory System
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00067openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/mm.2013.9openalex-snapshot
IBM zEC12: The Third-Generation High-Frequency Mainframe Microprocessor
inferred← citeshttps://doi.org/10.1109/mm.2020.3017107openalex-snapshot
History of IBM Z Mainframe Processors
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SAM: Optimizing Multithreaded Cores for Speculative Parallelism
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Forgive-TM: Supporting Lazy Conflict Detection In Eager Hardware Transactional Memory
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Improving Performance of Transactional Applications through Adaptive Transactional Memory
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Experiences with Disjoint Data Structures in a New Hardware Transactional Memory System
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Serialization Management for Best-Effort Hardware Transactional Memory
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FGSCM: A Fine-Grained Approach to Transactional Lock Elision
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Synchronization Strategies on Many-Core SMT Systems
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Protecting Private Keys against Memory Disclosure Attacks Using Hardware Transactional Memory
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High-Level Synthesis of Transactional Memory
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AI accelerator on IBM Telum processor
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GPU computing architecture for irregular parallelism
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Guided Automatic Binary Parallelisation
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But how do we really debug transactional memory programs
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Concurrent Algorithms for Emerging Hardware Platforms
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