On the public citation graph

Runtime-Guided Cache Coherence Optimizations in Multi-core Architectures

https://doi.org/10.1109/ipdps.2014.71

0 signed · 50 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.

Claim with ORCID

Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.

See reference health

What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-3-540-79561-2_9openalex-snapshot

Evaluation of OpenMP Task Scheduling Strategies

inferredcites →https://doi.org/10.1109/12.256449openalex-snapshot

Cache invalidation patterns in shared-memory multiprocessors

inferredcites →https://doi.org/10.1109/dsd.2008.45openalex-snapshot

A Look-Ahead Task Management Unit for Embedded Multi-Core Architectures

inferredcites →https://doi.org/10.1109/icpp.2013.64openalex-snapshot

Efficient Forwarding of Producer-Consumer Data in Task-Based Programs

inferredcites →https://doi.org/10.1109/ipdps.2009.5161079openalex-snapshot

Work-first and help-first scheduling policies for async-finish task parallelism

inferredcites →https://doi.org/10.1109/micro.2010.13openalex-snapshot

Task Superscalar: An Out-of-Order Task Pipeline

inferredcites →https://doi.org/10.1109/pact.2007.4336195openalex-snapshot

Architectural Support for the Stream Execution Model on General-Purpose Processors

inferredcites →https://doi.org/10.1109/pact.2011.21openalex-snapshot

DeNovo: Rethinking the Memory Hierarchy for Disciplined Parallelism

inferredcites →https://doi.org/10.1142/s0129626406002599openalex-snapshot

CacheFlow: Cache Optimizations for Data Driven Multithreading

inferredcites →https://doi.org/10.1142/s0129626411000151openalex-snapshot

OmpSs: A PROPOSAL FOR PROGRAMMING HETEROGENEOUS MULTI-CORE ARCHITECTURES

inferredcites →https://doi.org/10.1145/1250662.1250683openalex-snapshot

Carbon

inferredcites →https://doi.org/10.1145/161541.161544openalex-snapshot

Cooperative shared memory

inferredcites →https://doi.org/10.1145/165123.165146openalex-snapshot

Adaptive cache coherency for detecting migratory shared data

inferredcites →https://doi.org/10.1145/1736020.1736055openalex-snapshot

Flexible architectural support for fine-grain scheduling

inferredcites →https://doi.org/10.1145/173682.165147openalex-snapshot

An adaptive cache coherence protocol optimized for migratory sharing

inferredcites →https://doi.org/10.1145/192007.192028openalex-snapshot

Combined performance gains of simple cache protocol extensions

inferredcites →https://doi.org/10.1145/2024716.2024718openalex-snapshot

The gem5 simulator

inferredcites →https://doi.org/10.1145/223982.223995openalex-snapshot

Dynamic self-invalidation

inferredcites →https://doi.org/10.1145/225830.223995openalex-snapshot

Dynamic self-invalidation

inferredcites →https://doi.org/10.1145/2464996.2465443openalex-snapshot

Prefetching and cache management using task lifetimes

inferredcites →https://doi.org/10.1145/2486159.2486175openalex-snapshot

Locality-aware task management for unstructured parallelism

inferredcites →https://doi.org/10.1145/2503210.2503224openalex-snapshot

Location-aware cache management for many-core processors with deep cache hierarchy

inferredcites →https://doi.org/10.1145/264107.264206openalex-snapshot

The SGI Origin

inferredcites →https://doi.org/10.1145/279358.279386openalex-snapshot

Using prediction to accelerate coherence protocols

inferredcites →https://doi.org/10.1145/279361.279386openalex-snapshot

Using prediction to accelerate coherence protocols

inferredcites →https://doi.org/10.1145/341800.341801openalex-snapshot

The data locality of work stealing

inferredcites →https://doi.org/10.1145/342001.339669openalex-snapshot

Selective, accurate, and timely self-invalidation using last-touch prediction

inferredcites →https://doi.org/10.1145/384286.264206openalex-snapshot

The SGI Origin

inferredcites →https://doi.org/10.1145/99163.99182openalex-snapshot

Munin: distributed shared memory based on type-specific memory coherence

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-319-64203-1_18openalex-snapshot

Runtime-Assisted Shared Cache Insertion Policies Based on Re-reference Intervals

inferred← citeshttps://doi.org/10.1007/978-3-319-92040-5_20openalex-snapshot

TaskGenX: A Hardware-Software Proposal for Accelerating Task Parallelism

inferred← citeshttps://doi.org/10.1007/978-3-662-48096-0_2openalex-snapshot

Runtime-Aware Architectures

inferred← citeshttps://doi.org/10.1109/hpca.2016.7446101openalex-snapshot

RADAR: Runtime-assisted dead region management for last-level caches

inferred← citeshttps://doi.org/10.1109/ipdps.2016.49openalex-snapshot

CATA: Criticality Aware Task Acceleration for Multicore Processors

inferred← citeshttps://doi.org/10.1109/lca.2016.2606593openalex-snapshot

Runtime-Assisted Global Cache Management for Task-Based Parallel Programs

inferred← citeshttps://doi.org/10.1109/pact.2015.26openalex-snapshot

Runtime-Guided Management of Scratchpad Memories in Multicore Architectures

inferred← citeshttps://doi.org/10.1109/sc41404.2022.00085openalex-snapshot

TD-NUCA: Runtime Driven Management of NUCA Caches in Task Dataflow Programming Models

inferred← citeshttps://doi.org/10.1109/tpds.2017.2787123openalex-snapshot

Reducing Cache Coherence Traffic with a NUMA-Aware Runtime Approach

inferred← citeshttps://doi.org/10.1145/2807591.2807625openalex-snapshot

Runtime-driven shared last-level cache management for task-parallel programs

inferred← citeshttps://doi.org/10.1145/2884045.2884055openalex-snapshot

Runtime aware architectures

inferred← citeshttps://doi.org/10.1145/2967938.2967962openalex-snapshot

Reducing Cache Coherence Traffic with Hierarchical Directory Cache and NUMA-Aware Runtime Scheduling

inferred← citeshttps://doi.org/10.1145/3079079.3079101openalex-snapshot

libPRISM

inferred← citeshttps://doi.org/10.1145/3205289.3205310openalex-snapshot

Reducing Data Movement on Large Shared Memory Systems by Exploiting Computation Dependencies

inferred← citeshttps://doi.org/10.1145/3234337openalex-snapshot

Global Dead-Block Management for Task-Parallel Programs

inferred← citeshttps://doi.org/10.14529/jsfi140102openalex-snapshot

Runtime-Aware Architectures: A First Approach

inferred← citeshttps://doi.org/10.5821/dissertation-2117-125307openalex-snapshot

Exploiting asymmetric multi-core systems with flexible system software

inferred← citeshttps://doi.org/10.5821/dissertation-2117-125507openalex-snapshot

Hardware runtime management for task-based programming models

inferred← citeshttps://doi.org/10.5821/dissertation-2117-134744openalex-snapshot

Parallel architectures and runtime systems co-design for task-based programming models

inferred← citeshttps://doi.org/10.5821/dissertation-2117-166153openalex-snapshot

Exploiting task-based programming models for resilience

inferred← citeshttps://doi.org/10.5821/dissertation-2117-96004openalex-snapshot

Transparent management of scratchpad memories in shared memory programming models

Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.