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CATA: Criticality Aware Task Acceleration for Multicore Processors
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1002/cpe.1631openalex-snapshot
StarPU: a unified platform for task scheduling on heterogeneous multicore architectures
inferredcites →https://doi.org/10.1007/978-3-031-01721-6openalex-snapshot
Computer Architecture Techniques for Power-Efficiency
inferredcites →https://doi.org/10.1007/978-3-642-03869-3_80openalex-snapshot
StarPU: A Unified Platform for Task Scheduling on Heterogeneous Multicore Architectures
inferredcites →https://doi.org/10.1007/978-3-662-48096-0_2openalex-snapshot
Runtime-Aware Architectures
inferredcites →https://doi.org/10.1109/hpca.2008.4658633openalex-snapshot
System level analysis of fast, per-core DVFS using on-chip switching regulators
inferredcites →https://doi.org/10.1109/hpca.2012.6168942openalex-snapshot
Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chips
inferredcites →https://doi.org/10.1109/hpca.2014.6835969openalex-snapshot
Dynamic management of TurboMode in modern multi-core chips
inferredcites →https://doi.org/10.1109/icpp.2013.64openalex-snapshot
Efficient Forwarding of Producer-Consumer Data in Task-Based Programs
inferredcites →https://doi.org/10.1109/ipdps.2014.71openalex-snapshot
Runtime-Guided Cache Coherence Optimizations in Multi-core Architectures
inferredcites →https://doi.org/10.1109/isca.2008.8openalex-snapshot
Software-Controlled Priority Characterization of POWER5 Processor
inferredcites →https://doi.org/10.1109/l-ca.2011.36openalex-snapshot
Mitigating the Effects of Process Variation in Ultra-low Voltage Chip Multiprocessors using Dual Supply Voltages and Half-Speed Units
inferredcites →https://doi.org/10.1109/mascots.2013.75openalex-snapshot
Introducing DVFS-Management in a Full-System Simulator
inferredcites →https://doi.org/10.1109/micro.2006.49openalex-snapshot
Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches
inferredcites →https://doi.org/10.1109/micro.2010.13openalex-snapshot
Task Superscalar: An Out-of-Order Task Pipeline
inferredcites →https://doi.org/10.1109/micro.2012.36openalex-snapshot
MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP
inferredcites →https://doi.org/10.1109/pact.2011.7openalex-snapshot
A Unified Scheduler for Recursive and Task Dataflow Parallelism
inferredcites →https://doi.org/10.1109/sc.2006.55openalex-snapshot
Sequoia: Programming the Memory Hierarchy
inferredcites →https://doi.org/10.1109/sc.2012.71openalex-snapshot
Legion: Expressing locality and independence with logical regions
inferredcites →https://doi.org/10.1142/s0129626411000151openalex-snapshot
OmpSs: A PROPOSAL FOR PROGRAMMING HETEROGENEOUS MULTI-CORE ARCHITECTURES
inferredcites →https://doi.org/10.1145/1150019.1136493openalex-snapshot
Techniques for Multicore Thermal Management
inferredcites →https://doi.org/10.1145/1394608.1382157openalex-snapshot
Software-Controlled Priority Characterization of POWER5 Processor
inferredcites →https://doi.org/10.1145/1508244.1508274openalex-snapshot
Accelerating critical section execution with asymmetric multi-core architectures
inferredcites →https://doi.org/10.1145/1542275.1542304openalex-snapshot
Chunking parallel loops in the presence of synchronization
inferredcites →https://doi.org/10.1145/1555754.1555792openalex-snapshot
Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors
inferredcites →https://doi.org/10.1145/1735970.1736055openalex-snapshot
Flexible architectural support for fine-grain scheduling
inferredcites →https://doi.org/10.1145/1736020.1736055openalex-snapshot
Flexible architectural support for fine-grain scheduling
inferredcites →https://doi.org/10.1145/1787275.1787338openalex-snapshot
Interval-based models for run-time DVFS orchestration in superscalar processors
inferredcites →https://doi.org/10.1145/1952998.1952999openalex-snapshot
Fine-grained DVFS using on-chip regulators
inferredcites →https://doi.org/10.1145/2000417.2000424openalex-snapshot
Using a "codelet" program execution model for exascale machines
inferredcites →https://doi.org/10.1145/2150976.2151001openalex-snapshot
Bottleneck identification and scheduling in multithreaded applications
inferredcites →https://doi.org/10.1145/2464996.2465443openalex-snapshot
Prefetching and cache management using task lifetimes
inferredcites →https://doi.org/10.1145/2485922.2485936openalex-snapshot
Utility-based acceleration of multithreaded applications on asymmetric CMPs
inferredcites →https://doi.org/10.1145/2485922.2485949openalex-snapshot
A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness
inferredcites →https://doi.org/10.1145/2597917.2597932openalex-snapshot
Embracing heterogeneity with dynamic core boosting
inferredcites →https://doi.org/10.1145/2751205.2751235openalex-snapshot
Criticality-Aware Dynamic Task Scheduling for Heterogeneous Architectures
inferredcites →https://doi.org/10.1145/780822.781137openalex-snapshot
The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction
inferredcites →https://doi.org/10.14529/jsfi140102openalex-snapshot
Runtime-Aware Architectures: A First Approach
inferredcites →https://doi.org/10.2200/s00119ed1v01y200805cac004openalex-snapshot
Computer Architecture Techniques for Power-Efficiency
inferredcites →https://doi.org/10.5555/2388996.2389086openalex-snapshot
Legion: expressing locality and independence with logical regions
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-030-85665-6_37openalex-snapshot
PrioRAT: Criticality-Driven Prioritization Inside the On-Chip Memory Hierarchy
inferred← citeshttps://doi.org/10.1109/hpca.2018.00033openalex-snapshot
Architectural Support for Task Dependence Management with Flexible Software Scheduling
inferred← citeshttps://doi.org/10.1109/hpca.2019.00033openalex-snapshot
Adaptive Voltage/Frequency Scaling and Core Allocation for Balanced Energy and Performance on Multicore CPUs
inferred← citeshttps://doi.org/10.1109/ipdps57955.2024.00036openalex-snapshot
SWEEP: Adaptive Task Scheduling for Exploring Energy Performance Trade-offs
inferred← citeshttps://doi.org/10.1109/sbac-pad55451.2022.00043openalex-snapshot
STEER: Asymmetry-aware Energy Efficient Task Scheduler for Cluster-based Multicore Architectures
inferred← citeshttps://doi.org/10.1109/sc.2018.00038openalex-snapshot
Runtime-Assisted Cache Coherence Deactivation in Task Parallel Programs
inferred← citeshttps://doi.org/10.1109/sc41404.2022.00085openalex-snapshot
TD-NUCA: Runtime Driven Management of NUCA Caches in Task Dataflow Programming Models
inferred← citeshttps://doi.org/10.1109/tc.2020.2980230openalex-snapshot
Intelligent Adaptation of Hardware Knobs for Improving Performance and Power Consumption
inferred← citeshttps://doi.org/10.1109/tcad.2020.3013076openalex-snapshot
VisSched: An Auction-Based Scheduler for Vision Workloads on Heterogeneous Processors
inferred← citeshttps://doi.org/10.1145/3205289.3205312openalex-snapshot
Runtime-Guided Management of Stacked DRAM Memories in Task Parallel Programs
inferred← citeshttps://doi.org/10.1145/3447818.3461616openalex-snapshot
Task-graph scheduling extensions for efficient synchronization and communication
inferred← citeshttps://doi.org/10.1145/3510422openalex-snapshot
ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes
inferred← citeshttps://doi.org/10.1145/3774934.3786452openalex-snapshot
Waste-Efficient Work Stealing
inferred← citeshttps://doi.org/10.5821/dissertation-2117-125307openalex-snapshot
Exploiting asymmetric multi-core systems with flexible system software
inferred← citeshttps://doi.org/10.5821/dissertation-2117-134618openalex-snapshot
Towards resource-aware computing for task-based runtimes and parallel architectures
inferred← citeshttps://doi.org/10.5821/dissertation-2117-134744openalex-snapshot
Parallel architectures and runtime systems co-design for task-based programming models
inferred← citeshttps://doi.org/10.5821/dissertation-2117-166153openalex-snapshot
Exploiting task-based programming models for resilience
inferred← citeshttps://doi.org/10.5821/dissertation-2117-335422openalex-snapshot
Runtime-assisted optimizations in the on-chip memory hierarchy
inferred← citeshttps://doi.org/10.5821/dissertation-2117-336238openalex-snapshot
Runtime-assisted coherent caching
inferred← citeshttps://doi.org/10.5821/dissertation-2117-351088openalex-snapshot
Novel techniques to improve the performance and the energy of vector architectures
inferred← citeshttps://doi.org/10.5821/dissertation-2117-367546openalex-snapshot
Exploiting data locality in cache-coherent NUMA systems
inferred← citeshttps://doi.org/10.5821/dissertation-2117-413894openalex-snapshot
Hardware knob coordination in multi-threaded systems
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