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PRO: Progress Aware GPU Warp Scheduling Algorithm
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-642-54807-9_8openalex-snapshot
Taming Control Divergence in GPUs through Control Flow Linearization
inferredcites →https://doi.org/10.1109/hpca.2011.5749714openalex-snapshot
Thread block compaction for efficient SIMT control flow
inferredcites →https://doi.org/10.1109/hpca.2013.6522352openalex-snapshot
The dual-path execution model for efficient GPU control flow
inferredcites →https://doi.org/10.1109/hpca.2014.6835939openalex-snapshot
Warp-level divergence in GPUs: Characterization, impact, and mitigation
inferredcites →https://doi.org/10.1109/iiswc.2009.5306797openalex-snapshot
Rodinia: A benchmark suite for heterogeneous computing
inferredcites →https://doi.org/10.1109/ispass.2009.4919648openalex-snapshot
Analyzing CUDA workloads using a detailed GPU simulator
inferredcites →https://doi.org/10.1109/micro.2007.12openalex-snapshot
Microarchitectural Design Space Exploration Using an Architecture-Centric Approach
inferredcites →https://doi.org/10.1109/micro.2007.30openalex-snapshot
Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow
inferredcites →https://doi.org/10.1109/micro.2012.16openalex-snapshot
Cache-Conscious Wavefront Scheduling
inferredcites →https://doi.org/10.1109/pact.2013.6618806openalex-snapshot
Neither more nor less: optimizing thread-level parallelism for GPGPUs
inferredcites →https://doi.org/10.1145/1815961.1815992openalex-snapshot
Dynamic warp subdivision for integrated branch and memory divergence tolerance
inferredcites →https://doi.org/10.1145/2000064.2000093openalex-snapshot
Energy-efficient mechanisms for managing thread context in throughput processors
inferredcites →https://doi.org/10.1145/2155620.2155656openalex-snapshot
Improving GPU performance via large warps and two-level warp scheduling
inferredcites →https://doi.org/10.1145/2155620.2155676openalex-snapshot
SIMD re-convergence at thread frontiers
inferredcites →https://doi.org/10.1145/2485922.2485951openalex-snapshot
Orchestrated scheduling and prefetching for GPGPUs
inferredcites →https://doi.org/10.1145/2540708.2540718openalex-snapshot
Divergence-aware warp scheduling
inferredcites →https://doi.org/10.5555/2523721.2523745openalex-snapshot
Neither more nor less: optimizing thread-level parallelism for GPGPUs
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-030-25636-4_9openalex-snapshot
Compiler Generated Progress Estimation for OpenMP Programs
inferred← citeshttps://doi.org/10.1016/j.jpdc.2018.11.012openalex-snapshot
A survey of architectural approaches for improving GPGPU performance, programmability and heterogeneity
inferred← citeshttps://doi.org/10.1016/j.micpro.2025.105203openalex-snapshot
Time-predictable warp scheduling in a GPU
inferred← citeshttps://doi.org/10.1109/dsd64264.2024.00053openalex-snapshot
Coordinating the Fetch and Issue Warp Schedulers to Increase the Timing Predictability of GPUs
inferred← citeshttps://doi.org/10.1109/icicat68430.2025.11414460openalex-snapshot
Reprogrammable Instruction Set Architecture for Microprocessing Devices
inferred← citeshttps://doi.org/10.1109/intelcis.2015.7397284openalex-snapshot
A survey of techniques for warp scheduling in GPUs
inferred← citeshttps://doi.org/10.1109/ipdps65963.2026.00053openalex-snapshot
CACWS: Congestion-Aware Coordinated Warp Scheduler for Partitioned GPGPU
inferred← citeshttps://doi.org/10.1109/isca59077.2024.00075openalex-snapshot
Memento: An Adaptive, Compiler-Assisted Register File Cache for GPUs
inferred← citeshttps://doi.org/10.1109/iss1.2019.8908051openalex-snapshot
Improving GPGPU Performance Using Efficient Scheduling
inferred← citeshttps://doi.org/10.1109/lca.2015.2478778openalex-snapshot
Studying Inter-Warp Divergence Aware Execution on GPUs
inferred← citeshttps://doi.org/10.1109/pdp2018.2018.00061openalex-snapshot
SAWS: Simple and Adaptive Warp Scheduling for Improved Performance in Throughput Processors
inferred← citeshttps://doi.org/10.1109/socc62300.2024.10737822openalex-snapshot
MCLB: Dynamic Load Balancing and Implications on GPU Memory Controllers
inferred← citeshttps://doi.org/10.1109/tc.2017.2705678openalex-snapshot
Thread Criticality Assisted Replication and Migration for Chip Multiprocessor Caches
inferred← citeshttps://doi.org/10.1109/tc.2026.3688446openalex-snapshot
CAPA: A Framework for Contention-Aware and Progress-Aware Multi-Core Real-Time Systems
inferred← citeshttps://doi.org/10.17760/d20213291openalex-snapshot
Inter-warp divergence aware execution on GPUs
inferred← citeshttps://doi.org/10.4230/lipics.ecrts.2020.3openalex-snapshot
PAStime: Progress-Aware Scheduling for Time-Critical Computing
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