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Cache-Conscious Wavefront Scheduling
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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Wikipedia workload analysis for decentralized hosting
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CACTI: an enhanced cache access and cycle time model
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Thread block compaction for efficient SIMT control flow
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Rodinia: A benchmark suite for heterogeneous computing
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Many-Core vs. Many-Thread Machines: Stay Away From the Valley
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ASR: Adaptive Selective Replication for CMP Caches
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Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches
inferredcites →https://doi.org/10.1109/micro.2007.12openalex-snapshot
Microarchitectural Design Space Exploration Using an Architecture-Centric Approach
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Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow
inferredcites →https://doi.org/10.1109/micro.2010.39openalex-snapshot
Memory Latency Reduction via Thread Throttling
inferredcites →https://doi.org/10.1109/micro.2010.44openalex-snapshot
Many-Thread Aware Prefetching Mechanisms for GPGPU Applications
inferredcites →https://doi.org/10.1109/mm.2008.31openalex-snapshot
NVIDIA Tesla: A Unified Graphics and Computing Architecture
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Dark Silicon and the End of Multicore Scaling
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Templates for the Solution of Linear Systems: Building Blocks for Iterative Methods
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Using page residency to balance tradeoffs in tracing garbage collection
inferredcites →https://doi.org/10.1145/1250662.1250709openalex-snapshot
Adaptive insertion policies for high performance caching
inferredcites →https://doi.org/10.1145/1454115.1454145openalex-snapshot
Adaptive insertion policies for managing shared caches
inferredcites →https://doi.org/10.1145/1735970.1736036openalex-snapshot
Addressing shared resource contention in multicore processors via scheduling
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Addressing shared resource contention in multicore processors via scheduling
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Tracing garbage collection on highly parallel platforms
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High performance cache replacement using re-reference interval prediction (RRIP)
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Dynamic warp subdivision for integrated branch and memory divergence tolerance
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Energy-efficient mechanisms for managing thread context in throughput processors
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Dark silicon and the end of multicore scaling
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inferredcites →https://doi.org/10.1145/2304576.2304582openalex-snapshot
Characterizing and improving the use of demand-fetched caches in GPUs
inferredcites →https://doi.org/10.1145/2312005.2312049openalex-snapshot
Cache-conscious scheduling of streaming applications
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Improving direct-mapped cache performance by the addition of a small fully-associative cache prefetch buffers
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A study of replacement algorithms for a virtual-storage computer
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Accelerating GPU accelerators through neural algorithmic transformation
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Quantifying the performance and energy efficiency of advanced cache indexing for GPGPU computing
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Early miss prediction based periodic cache bypassing for high performance GPUs
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Virtual-Cache: A cache-line borrowing technique for efficient GPU cache architectures
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Time-predictable warp scheduling in a GPU
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A comprehensive survey on multi-GPU systems
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Simulating heterogeneous behaviours in complex systems on GPUs
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Application aware Scalable Architecture for GPGPU
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Locality‐protected cache allocation scheme with low overhead on GPUs
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Analyzing GCN Aggregation on GPU
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CAMO: A novel cache management organization for GPGPUs
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TwinKernels: An execution model to improve GPU hardware scheduling at compile time
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L2 Cache Access Pattern Analysis using Static Profiling of an Application
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An efficient STT-RAM last level cache architecture for GPUs
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VISTA: Optimizing GPU Scheduling through Versatile Locality-Aware Data Sharing
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HIVE: A High-Priority Victim Cache for Accelerating GPU Memory Accesses
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Performance-Based and Aging-Aware Resource Allocation for Concurrent GPU Applications
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Coordinating the Fetch and Issue Warp Schedulers to Increase the Timing Predictability of GPUs
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The dual-path execution model for efficient GPU control flow
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A scalable multi-path microarchitecture for efficient GPU control flow
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Improving GPGPU resource utilization through alternative thread block scheduling
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MRPB: Memory request prioritization for massively parallel processors
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Warp-level divergence in GPUs: Characterization, impact, and mitigation
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A detailed GPU cache model based on reuse distance theory
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GPUdmm: A high-performance and memory-oblivious GPU architecture using dynamic memory management
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Coordinated static and dynamic cache bypassing for GPUs
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Priority-based cache allocation in throughput processors
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WIR: Warp Instruction Reuse to Minimize Repeated Computations in GPUs
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Dynamic front-end sharing in graphics processing units
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Effective hardware-level thread synchronization for high performance and power efficiency in application specific multi-threaded embedded processors
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IACM: Integrated adaptive cache management for high-performance and energy-efficient GPGPU computing
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ONAC: Optimal number of active cores detector for energy efficient GPU computing
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BACM: Barrier-Aware Cache Management for Irregular Memory-Intensive GPGPU Workloads
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CART: Cache Access Reordering Tree for Efficient Cache and Memory Accesses in GPUs
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BLPP: Improving the Performance of GPGPUs with Heterogeneous Memory through Bandwidth- and Latency-Aware Page Placement
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AICAWS: Arithmetic Intensity Based Cache-Conscious Adaptive Warp Scheduler
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Elastic Search in Cache Based Service Management for Healthcare Automation
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Selectively GPU Cache Bypassing for Un-Coalesced Loads
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LWSDP: Locality-Aware Warp Scheduling and Dynamic Data Prefetching Co-design in the Per-SM Private Cache of GPGPUs
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Perf-Sat: Runtime Detection of Performance Saturation for GPGPU Applications
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ID-cache: instruction and memory divergence based cache management for GPUs
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A Survey of Caching Techniques for General Purpose Graphics Processing Units
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A survey of techniques for warp scheduling in GPUs
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PRO: Progress Aware GPU Warp Scheduling Algorithm
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X: A Comprehensive Analytic Model for Parallel Machines
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CTA-Aware Prefetching and Scheduling for GPU
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CIAO: Cache Interference-Aware Throughput-Oriented Architecture and Scheduling for GPUs
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Millipede: Die-Stacked Memory Optimizations for Big Data Machine Learning Analytics
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Intra-Cluster Coalescing to Reduce GPU NoC Pressure
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A Fine-grained Prefetching Scheme for DGEMM Kernels on GPU with Auto-tuning Compatibility
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CACWS: Congestion-Aware Coordinated Warp Scheduler for Partitioned GPGPU
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APRES: Improving Cache Efficiency by Exploiting Load Characteristics on GPUs
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Transparent Offloading and Mapping (TOM): Enabling Programmer-Transparent Near-Data Processing in GPU Systems
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LaPerm: Locality Aware Scheduler for Dynamic Parallelism on GPUs
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Virtual Thread: Maximizing Thread-Level Parallelism beyond GPU Scheduling Limit
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Get Out of the Valley: Power-Efficient Address Mapping for GPUs
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Scheduling Page Table Walks for Irregular GPU Applications
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The Locality Descriptor: A Holistic Cross-Layer Abstraction to Express Data Locality In GPUs
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Generic System Calls for GPUs
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Accel-Sim: An Extensible Simulation Framework for Validated GPU Modeling
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GhOST: a GPU Out-of-Order Scheduling Technique for Stall Reduction
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Memento: An Adaptive, Compiler-Assisted Register File Cache for GPUs
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sCROOGe: Circuit-level Design and Optimization Framework for RISC-V Out-of-Order GPUs
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Bank stealing for conflict mitigation in GPGPU Register File
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Exploring the Relation between Monolithic 3D L1 GPU Cache Capacity and Warp Scheduling Efficiency
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Understanding the tradeoffs between software-managed vs. hardware-managed caches in GPUs
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DRAW: investigating benefits of adaptive fetch group size on GPU
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EmerGPU: Understanding and mitigating resonance-induced voltage noise in GPU architectures
inferred← citeshttps://doi.org/10.1109/ispass.2017.7975295openalex-snapshot
Evaluating and mitigating bandwidth bottlenecks across the memory hierarchy in GPUs
inferred← citeshttps://doi.org/10.1109/ispass51385.2021.00037openalex-snapshot
Characterizing Massively Parallel Polymorphism
inferred← citeshttps://doi.org/10.1109/ispass69572.2026.00065openalex-snapshot
Macsim Mini: A Lightweight Cycle-Level GPU Simulator for Architecture Education
inferred← citeshttps://doi.org/10.1109/ispdc.2016.12openalex-snapshot
Applying Victim Cache in High Performance GPGPU Computing
inferred← citeshttps://doi.org/10.1109/ispdc.2017.17openalex-snapshot
Contention-Aware Selective Caching to Mitigate Intra-Warp Contention on GPUs
inferred← citeshttps://doi.org/10.1109/itc-cscc66376.2025.11137781openalex-snapshot
Tournament Warp Scheduling: A Dynamic Policy Selector Exploiting Sub-cores in GPUs
inferred← citeshttps://doi.org/10.1109/lca.2014.2359882openalex-snapshot
Adaptive Cache and Concurrency Allocation on GPGPUs
inferred← citeshttps://doi.org/10.1109/lca.2015.2435709openalex-snapshot
Inter-Core Locality Aware Memory Scheduling
inferred← citeshttps://doi.org/10.1109/lca.2015.2478778openalex-snapshot
Studying Inter-Warp Divergence Aware Execution on GPUs
inferred← citeshttps://doi.org/10.1109/lca.2016.2611663openalex-snapshot
LA-LLC: Inter-Core Locality-Aware Last-Level Cache to Exploit Many-to-Many Traffic in GPGPUs
inferred← citeshttps://doi.org/10.1109/lca.2017.2693371openalex-snapshot
Improving GPGPU Performance via Cache Locality Aware Thread Block Scheduling
inferred← citeshttps://doi.org/10.1109/lca.2019.2951161openalex-snapshot
LOOG: Improving GPU Efficiency With Light-Weight Out-Of-Order Execution
inferred← citeshttps://doi.org/10.1109/mcsoc.2014.45openalex-snapshot
A Cache Aware Multithreading Decision Scheme on GPGPUs
inferred← citeshttps://doi.org/10.1109/micro.2014.11openalex-snapshot
Adaptive Cache Management for Energy-Efficient GPU Computing
inferred← citeshttps://doi.org/10.1109/micro.2014.16openalex-snapshot
Equalizer: Dynamic Tuning of GPU Resources for Efficient Execution
inferred← citeshttps://doi.org/10.1109/micro.2014.59openalex-snapshot
GPUMech: GPU Performance Modeling Technique Based on Interval Analysis
inferred← citeshttps://doi.org/10.1109/micro.2014.62openalex-snapshot
Managing GPU Concurrency in Heterogeneous Architectures
inferred← citeshttps://doi.org/10.1109/micro.2016.7783714openalex-snapshot
MIMD synchronization on SIMT architectures
inferred← citeshttps://doi.org/10.1109/micro.2016.7783717openalex-snapshot
Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs
inferred← citeshttps://doi.org/10.1109/micro.2016.7783718openalex-snapshot
Zorua: A holistic approach to resource virtualization in GPUs
inferred← citeshttps://doi.org/10.1109/micro.2016.7783719openalex-snapshot
GRAPE: Minimizing energy for GPU applications with performance requirements
inferred← citeshttps://doi.org/10.1109/micro.2018.00037openalex-snapshot
FineReg: Fine-Grained Register File Management for Augmenting GPU Throughput
inferred← citeshttps://doi.org/10.1109/micro.2018.00039openalex-snapshot
Voltage-Stacked GPUs: A Control Theory Driven Cross-Layer Solution for Practical Voltage Stacking in GPUs
inferred← citeshttps://doi.org/10.1109/micro50266.2020.00082openalex-snapshot
Selective Replication in Memory-Side GPU Caches
inferred← citeshttps://doi.org/10.1109/micro50266.2020.00083openalex-snapshot
Deterministic Atomic Buffering
inferred← citeshttps://doi.org/10.1109/micro50266.2020.00086openalex-snapshot
Locality-Centric Data and Threadblock Management for Massive GPUs
inferred← citeshttps://doi.org/10.1109/micro56248.2022.00029openalex-snapshot
Morpheus: Extending the Last Level Cache Capacity in GPU Systems Using Idle GPU Core Resources
inferred← citeshttps://doi.org/10.1109/micro56248.2022.00030openalex-snapshot
Featherweight Soft Error Resilience for GPUs
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00022openalex-snapshot
HyFiSS: A Hybrid Fidelity Stall-Aware Simulator for GPGPUs
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00057openalex-snapshot
Concurrency-Aware Register Stacks for Efficient GPU Function Calls
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00070openalex-snapshot
Uncovering Real GPU NoC Characteristics: Implications on Interconnect Architecture
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00081openalex-snapshot
LIBRA: Memory Bandwidth- and Locality-Aware Parallel Tile Rendering
inferred← citeshttps://doi.org/10.1109/mm.2013.24openalex-snapshot
Cache-Conscious Thread Scheduling for Massively Multithreaded Processors
inferred← citeshttps://doi.org/10.1109/mm.2015.44openalex-snapshot
Address Translation for Throughput-Oriented Accelerators
inferred← citeshttps://doi.org/10.1109/nas.2017.8026851openalex-snapshot
DD-L1D: Improving the Decoupled L1D Efficiency for GPU Architecture
inferred← citeshttps://doi.org/10.1109/paap54281.2021.9720477openalex-snapshot
Reducing TLB Miss Penalty on GPUs via Unified Multi-level PWB and PWC
inferred← citeshttps://doi.org/10.1109/pact.2013.6618813openalex-snapshot
Reshaping cache misses to improve row-buffer locality in multicore systems
inferred← citeshttps://doi.org/10.1109/pact.2015.31openalex-snapshot
Phase Aware Warp Scheduling: Mitigating Effects of Phase Behavior in GPGPU Applications
inferred← citeshttps://doi.org/10.1109/pact.2015.38openalex-snapshot
Exploiting Inter-Warp Heterogeneity to Improve GPGPU Performance
inferred← citeshttps://doi.org/10.1109/pact.2015.60openalex-snapshot
Integrating 3D Resistive Memory Cache into GPGPU for Energy-Efficient Data Processing
inferred← citeshttps://doi.org/10.1109/pact.2017.37openalex-snapshot
SAM: Optimizing Multithreaded Cores for Speculative Parallelism
inferred← citeshttps://doi.org/10.1109/pact.2019.00028openalex-snapshot
Analyzing and Leveraging Remote-Core Bandwidth for Enhanced Performance in GPUs
inferred← citeshttps://doi.org/10.1109/pact.2019.00033openalex-snapshot
Adaptive Task Aggregation for High-Performance Sparse Solvers on GPUs
inferred← citeshttps://doi.org/10.1109/pccc.2016.7820638openalex-snapshot
A reuse distance based performance analysis on GPU L1 data cache
inferred← citeshttps://doi.org/10.1109/pdp2018.2018.00069openalex-snapshot
Studying Victim Caches in GPUs
inferred← citeshttps://doi.org/10.1109/pdp50117.2020.00051openalex-snapshot
Selective Caching: Avoiding Performance Valleys in Massively Parallel Architectures
inferred← citeshttps://doi.org/10.1109/sbcci53441.2021.9529986openalex-snapshot
ETCG: Energy-Aware CPU Thread Throttling for CPU-GPU Collaborative Environments
inferred← citeshttps://doi.org/10.1109/sbesc53686.2021.9628345openalex-snapshot
ETCF – Energy-Aware CPU Thread Throttling and Workload Balancing Framework for CPU-FPGA Collaborative Environments
inferred← citeshttps://doi.org/10.1109/sc.2014.16openalex-snapshot
Managing DRAM Latency Divergence in Irregular GPGPU Applications
inferred← citeshttps://doi.org/10.1109/socc56010.2022.9908120openalex-snapshot
Cache-locality Based Adaptive Warp Scheduling for Neural Network Acceleration on GPGPUs
inferred← citeshttps://doi.org/10.1109/tc.2015.2417545openalex-snapshot
Energy-Efficient eDRAM-Based On-Chip Storage Architecture for GPGPUs
inferred← citeshttps://doi.org/10.1109/tc.2017.2690855openalex-snapshot
An Energy-Efficient GPGPU Register File Architecture Using Racetrack Memory
inferred← citeshttps://doi.org/10.1109/tc.2017.2776272openalex-snapshot
CRAT: Enabling Coordinated Register Allocation and Thread-Level Parallelism Optimization for GPUs
inferred← citeshttps://doi.org/10.1109/tc.2018.2813379openalex-snapshot
WASP: Selective Data Prefetching with Monitoring Runtime Warp Progress on GPUs
inferred← citeshttps://doi.org/10.1109/tc.2018.2878671openalex-snapshot
Adaptive Cooperation of Prefetching and Warp Scheduling on GPUs
inferred← citeshttps://doi.org/10.1109/tc.2019.2895036openalex-snapshot
Intra-Cluster Coalescing and Distributed-Block Scheduling to Reduce GPU NoC Pressure
inferred← citeshttps://doi.org/10.1109/tc.2019.2907591openalex-snapshot
Efficient Management of Cache Accesses to Boost GPGPU Memory Subsystem Performance
inferred← citeshttps://doi.org/10.1109/tc.2020.3026043openalex-snapshot
MIPSGPU: Minimizing Pipeline Stalls for GPUs With Non-Blocking Execution
inferred← citeshttps://doi.org/10.1109/tcad.2015.2424962openalex-snapshot
An Efficient Compiler Framework for Cache Bypassing on GPUs
inferred← citeshttps://doi.org/10.1109/tcad.2017.2764886openalex-snapshot
Optimizing Cache Bypassing and Warp Scheduling for GPUs
inferred← citeshttps://doi.org/10.1109/tcad.2019.2946808openalex-snapshot
FRF: Toward Warp-Scheduler Friendly STT-RAM/SRAM Fine-Grained Hybrid GPGPU Register File Design
inferred← citeshttps://doi.org/10.1109/tcsi.2019.2933245openalex-snapshot
Kernel-Based Resource Allocation for Improving GPU Throughput While Minimizing the Activity Divergence of SMs
inferred← citeshttps://doi.org/10.1109/tnano.2019.2928268openalex-snapshot
Performance and Aging Aware Resource Allocation for Concurrent GPU Applications Under Process Variation
inferred← citeshttps://doi.org/10.1109/tpds.2016.2627560openalex-snapshot
SACAT: Streaming-Aware Conflict-Avoiding Thrashing-Resistant GPGPU Cache Management Scheme
inferred← citeshttps://doi.org/10.1109/tpds.2017.2704080openalex-snapshot
Dynamic Resizing on Active Warps Scheduler to Hide Operation Stalls on GPUs
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