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Write-Avoiding Algorithms
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1002/(sici)1096-9128(199704)9:4<255::aid-cpe250>3.0.co;2-2openalex-snapshot
SUMMA: scalable universal matrix multiplication algorithm
inferredcites →https://doi.org/10.1007/978-3-540-68552-4_16openalex-snapshot
Characterizing the Performance of Flash Memory Storage Devices and Its Impact on Algorithm Design
inferredcites →https://doi.org/10.1007/978-3-642-23397-5_10openalex-snapshot
Communication-Optimal Parallel 2.5D Matrix Multiplication and LU Factorization Algorithms
inferredcites →https://doi.org/10.1007/978-3-642-34862-4_2openalex-snapshot
Graph Expansion Analysis for Communication Costs of Fast Rectangular Matrix Multiplication
inferredcites →https://doi.org/10.1007/s11390-015-1509-2openalex-snapshot
A Survey of Phase Change Memory Systems
inferredcites →https://doi.org/10.1016/0304-3975(90)90188-nopenalex-snapshot
Communication complexity of PRAMs
inferredcites →https://doi.org/10.1016/j.future.2006.04.017openalex-snapshot
Communication-efficient parallel generic pairwise elimination
inferredcites →https://doi.org/10.1016/j.jpdc.2004.03.021openalex-snapshot
Communication lower bounds for distributed-memory matrix multiplication
inferredcites →https://doi.org/10.1017/s0962492914000038openalex-snapshot
Communication lower bounds and optimal algorithms for numerical linear algebra
inferredcites →https://doi.org/10.1090/s0002-9904-1949-09320-5openalex-snapshot
An inequality related to the isoperimetric inequality
inferredcites →https://doi.org/10.1109/icpp.2011.15openalex-snapshot
Cache Pirating: Measuring the Curse of the Shared Cache
inferredcites →https://doi.org/10.1109/ipdps.2012.89openalex-snapshot
Identifying Opportunities for Byte-Addressable Non-Volatile Memory in Extreme-Scale Scientific Applications
inferredcites →https://doi.org/10.1109/ipdps.2013.108openalex-snapshot
A Communication-Optimal N-Body Algorithm for Direct Interactions
inferredcites →https://doi.org/10.1109/jssc.2010.2084491openalex-snapshot
A 4 Mb LV MOS-Selected Embedded Phase Change Memory in 90 nm Standard CMOS Technology
inferredcites →https://doi.org/10.1109/sc.2014.35openalex-snapshot
A Computation- and Communication-Optimal Parallel Direct 3-Body Algorithm
inferredcites →https://doi.org/10.1109/tc.2013.11openalex-snapshot
Scheduling to Optimize Cache Utilization for Non-Volatile Main Memories
inferredcites →https://doi.org/10.1137/080731992openalex-snapshot
Communication-optimal Parallel and Sequential QR and LU Factorizations
inferredcites →https://doi.org/10.1137/090769156openalex-snapshot
Minimizing Communication in Numerical Linear Algebra
inferredcites →https://doi.org/10.1137/100788926openalex-snapshot
CALU: A Communication Optimal LU Factorization Algorithm
inferredcites →https://doi.org/10.1137/120881191openalex-snapshot
Avoiding Communication in Nonsymmetric Lanczos-Based Krylov Subspace Methods
inferredcites →https://doi.org/10.1145/1089733.1089735openalex-snapshot
Algorithms and data structures for flash memories
inferredcites →https://doi.org/10.1145/1555754.1555758openalex-snapshot
Architecting phase change memory as a scalable dram alternative
inferredcites →https://doi.org/10.1145/1669112.1669117openalex-snapshot
Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling
inferredcites →https://doi.org/10.1145/1810479.1810519openalex-snapshot
Low depth cache-oblivious algorithms
inferredcites →https://doi.org/10.1145/1815961.1815971openalex-snapshot
High performance cache replacement using re-reference interval prediction (RRIP)
inferredcites →https://doi.org/10.1145/1921659.1921669openalex-snapshot
Competitive analysis of flash memory algorithms
inferredcites →https://doi.org/10.1145/2395116.2395121openalex-snapshot
Graph expansion and communication costs of fast matrix multiplication
inferredcites →https://doi.org/10.1145/2429069.2429077openalex-snapshot
Cache and I/O efficent functional algorithms
inferredcites →https://doi.org/10.1145/2755573.2755604openalex-snapshot
Sorting with Asymmetric Read and Write Costs
inferredcites →https://doi.org/10.1145/2786.2793openalex-snapshot
Amortized efficiency of list update and paging rules
inferredcites →https://doi.org/10.1145/48529.48535openalex-snapshot
The input/output complexity of sorting and related problems
inferredcites →https://doi.org/10.1147/rd.386.0673openalex-snapshot
A high-performance matrix-multiplication algorithm on a distributed-memory parallel computer, using overlapped communication
inferredcites →https://doi.org/10.1147/sj.52.0078openalex-snapshot
A study of replacement algorithms for a virtual-storage computer
inferredcites →https://doi.org/10.21236/ada584726openalex-snapshot
Communication Lower Bounds and Optimal Algorithms for Programs that Reference Arrays - Part 1
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-319-68783-4_31openalex-snapshot
Efficient Subgraph Matching on Non-volatile Memory
inferred← citeshttps://doi.org/10.1007/s11390-023-3489-yopenalex-snapshot
Joint-Communication Optimal Matrix Multiplication with Asymmetric Memories
inferred← citeshttps://doi.org/10.1109/ipdps.2017.60openalex-snapshot
Language-Based Optimizations for Persistence on Nonvolatile Main Memory Systems
inferred← citeshttps://doi.org/10.1109/ipdps.2018.00041openalex-snapshot
Software-Hardware Managed Last-level Cache Allocation Scheme for Large-Scale NVRAM-Based Multicores Executing Parallel Data Analytics Applications
inferred← citeshttps://doi.org/10.1109/ipdps.2018.00081openalex-snapshot
Implicit Decomposition for Write-Efficient Connectivity Algorithms
inferred← citeshttps://doi.org/10.1109/ipdps.2019.00058openalex-snapshot
Revisiting the I/O-Complexity of Fast Matrix Multiplication with Recomputations
inferred← citeshttps://doi.org/10.1109/ipdpsw.2018.00120openalex-snapshot
Survey: Computational Models for Asymmetric Read and Write Costs
inferred← citeshttps://doi.org/10.1109/ispass51385.2021.00036openalex-snapshot
A Case Against Hardware Managed DRAM Caches for NVRAM Based Systems
inferred← citeshttps://doi.org/10.1109/nas.2017.8026862openalex-snapshot
hpFog: A FPGA-Based Fog Computing Platform
inferred← citeshttps://doi.org/10.1109/tgcn.2021.3122545openalex-snapshot
RtFog: A Real-Time FPGA-Based Fog Node With Remote Dynamically Reconfigurable Application Plane for Fog Analytics Redeployment
inferred← citeshttps://doi.org/10.1137/1.9781611976489.6openalex-snapshot
The Read-Only Semi-External Model
inferred← citeshttps://doi.org/10.1137/21m1395545openalex-snapshot
Performance of the Low-Rank TT-SVD for Large Dense Tensors on Modern MultiCore CPUs
inferred← citeshttps://doi.org/10.1145/2933057.2933124openalex-snapshot
How Emerging Memory Technologies Will Have You Rethinking Algorithm Design
inferred← citeshttps://doi.org/10.1145/2935764.2935767openalex-snapshot
Parallel Algorithms for Asymmetric Read-Write Costs
inferred← citeshttps://doi.org/10.1145/3210377.3210380openalex-snapshot
Parallel Write-Efficient Algorithms and Data Structures for Computational Geometry
inferred← citeshttps://doi.org/10.1145/3210377.3210381openalex-snapshot
The Parallel Persistent Memory Model
inferred← citeshttps://doi.org/10.1145/3284355openalex-snapshot
Common Tangents of Two Disjoint Polygons in Linear Time and Constant Workspace
inferred← citeshttps://doi.org/10.1145/3295500.3356200openalex-snapshot
Optimizing the data movement in quantum transport simulations via data-centric parallel programming
inferred← citeshttps://doi.org/10.1145/3295500.3357156openalex-snapshot
Soleil-X : Turbulence, Particles, and Radiation in the Regent Programming Language
inferred← citeshttps://doi.org/10.1145/3317550.3321433openalex-snapshot
Designing Far Memory Data Structures
inferred← citeshttps://doi.org/10.1145/3323165.3323169openalex-snapshot
Writeback-Aware Caching (Brief Announcement)
inferred← citeshttps://doi.org/10.1145/3409964.3461801openalex-snapshot
Efficient Online Weighted Multi-Level Paging
inferred← citeshttps://doi.org/10.1145/3712285.3759895openalex-snapshot
KAMI: Communication-Avoiding General Matrix Multiplication within a Single GPU
inferred← citeshttps://doi.org/10.1177/10943420251317994openalex-snapshot
Performance of linear solvers in tensor-train format on current multicore architectures
inferred← citeshttps://doi.org/10.48550/arxiv.1910.12310openalex-snapshot
Sage: Parallel Semi-Asymmetric Graph Algorithms for NVRAMs
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