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Cooperative Caching for Chip Multiprocessors
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Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-44587-0_1openalex-snapshot
SPEComp: A New Benchmark Suite for Measuring Parallel Computer Performance
inferredcites →https://doi.org/10.1109/2.156381openalex-snapshot
DDM-a cache-only memory architecture
inferredcites →https://doi.org/10.1109/2.982916openalex-snapshot
Simics: A full system simulation platform
inferredcites →https://doi.org/10.1109/90.851975openalex-snapshot
Summary cache: a scalable wide-area Web cache sharing protocol
inferredcites →https://doi.org/10.1109/hpca.1996.501196openalex-snapshot
A shared-bus control mechanism and a cache coherence protocol for a high-performance on-chip multiprocessor
inferredcites →https://doi.org/10.1109/hpca.2004.10017openalex-snapshot
Organizing the Last Line of Defense before Hitting the Memory Wall for CMPs
inferredcites →https://doi.org/10.1109/hpca.2005.17openalex-snapshot
Improving Multiple-CMP Systems Using Token Coherence
inferredcites →https://doi.org/10.1109/isca.1988.5212openalex-snapshot
On the inclusion properties for multi-level cache hierarchies
inferredcites →https://doi.org/10.1109/isca.2000.854398openalex-snapshot
Piranha: a scalable architecture based on single-chip multiprocessing
inferredcites →https://doi.org/10.1109/isca.2003.1206999openalex-snapshot
Token Coherence: decoupling performance and correctness
inferredcites →https://doi.org/10.1109/isca.2005.39openalex-snapshot
Optimizing Replication, Communication, and Capacity Allocation in CMPs
inferredcites →https://doi.org/10.1109/isca.2005.52openalex-snapshot
The V-Way Cache: Demand Based Associativity via Global Replacement
inferredcites →https://doi.org/10.1109/l-ca.2002.8openalex-snapshot
MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research
inferredcites →https://doi.org/10.1109/mc.2003.1178046openalex-snapshot
Simulating a $2M commercial server on a $2K PC
inferredcites →https://doi.org/10.1109/micro.2003.1253183openalex-snapshot
Distance associativity for high-performance energy-efficient non-uniform cache architectures
inferredcites →https://doi.org/10.1109/micro.2004.21openalex-snapshot
Managing Wire Delay in Large Chip-Multiprocessor Caches
inferredcites →https://doi.org/10.1109/mm.2005.35openalex-snapshot
Niagara: A 32-Way Multithreaded Sparc Processor
inferredcites →https://doi.org/10.1109/pact.2004.1342546openalex-snapshot
Fair cache sharing and partitioning in a chip multiprocessor architecture
inferredcites →https://doi.org/10.1109/tpds.2007.1091openalex-snapshot
A NUCA Substrate for Flexible CMP Cache Sharing
inferredcites →https://doi.org/10.1145/1105734.1105747openalex-snapshot
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
inferredcites →https://doi.org/10.1145/224056.224072openalex-snapshot
Implementing global memory management in a workstation cluster
inferredcites →https://doi.org/10.1145/232973.232982openalex-snapshot
Evaluation of design alternatives for a multiprocessor microprocessor
inferredcites →https://doi.org/10.1145/285930.285987openalex-snapshot
A low-overhead coherence solution for multiprocessors with private cache memories
inferredcites →https://doi.org/10.1145/55364.55397openalex-snapshot
A cache coherence approach for large multiprocessor systems
inferredcites →https://doi.org/10.1145/605397.605420openalex-snapshot
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
inferredcites →https://doi.org/10.1147/rd.452.0299openalex-snapshot
High-throughput coherence control and hardware messaging in Everest
inferredcites →https://doi.org/10.5555/1267638.1267657openalex-snapshot
Cooperative caching: using remote client memory to improve file system performance
inferredcites →https://doi.org/10.5555/645988.674164openalex-snapshot
Exploring the Design Space of Future CMPs
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/spe.956openalex-snapshot
Two‐phase trace‐driven simulation (TPTS): a fast multicore processor architecture simulation approach
inferred← citeshttps://doi.org/10.1007/978-3-642-03644-6_4openalex-snapshot
A Novel Cache Organization for Tiled Chip Multiprocessor
inferred← citeshttps://doi.org/10.1007/978-3-642-03869-3_30openalex-snapshot
Last Bank: Dealing with Address Reuse in Non-Uniform Cache Architecture for CMPs
inferred← citeshttps://doi.org/10.1007/978-3-642-15277-1_25openalex-snapshot
Power-Efficient Spilling Techniques for Chip Multiprocessors
inferred← citeshttps://doi.org/10.1007/978-3-642-15277-1_28openalex-snapshot
Thread Owned Block Cache: Managing Latency in Many-Core Architecture
inferred← citeshttps://doi.org/10.1007/978-3-642-54212-1_2openalex-snapshot
Collaborative Memories in Clusters: Opportunities and Challenges
inferred← citeshttps://doi.org/10.1007/s10766-010-0162-1openalex-snapshot
An Evaluation of an OS-Based Coherence Scheme for Tiled CMPs
inferred← citeshttps://doi.org/10.1007/s11227-015-1608-4openalex-snapshot
Locality-aware data replication in the last-level cache for large scale multicores
inferred← citeshttps://doi.org/10.1007/s11227-017-2024-8openalex-snapshot
Exploring grouped coherence for clustered hierarchical cache
inferred← citeshttps://doi.org/10.1007/s11227-019-02858-xopenalex-snapshot
FOS: a low-power cache organization for multicores
inferred← citeshttps://doi.org/10.1016/j.jpdc.2010.11.009openalex-snapshot
C-AMTE: A location mechanism for flexible cache management in chip multiprocessors
inferred← citeshttps://doi.org/10.1109/ccece.2009.5090119openalex-snapshot
Cooperative caching in power-aware chip-multiprocessors
inferred← citeshttps://doi.org/10.1109/ccgrid.2013.16openalex-snapshot
Flexible Capacity Partitioning in Many-Core Tiled CMPs
inferred← citeshttps://doi.org/10.1109/compcomm.2016.7925214openalex-snapshot
Replication-aware Cache Management for CMPs with private LLCs
inferred← citeshttps://doi.org/10.1109/dsd.2009.153openalex-snapshot
An Evaluation of Behaviors of S-NUCA CMPs Running Scientific Workload
inferred← citeshttps://doi.org/10.1109/dsd.2010.41openalex-snapshot
Re-NUCA: Boosting CMP Performance Through Block Replication
inferred← citeshttps://doi.org/10.1109/dsd.2011.99openalex-snapshot
Energy Behaviour of NUCA Caches in CMPs
inferred← citeshttps://doi.org/10.1109/dsd57027.2022.00043openalex-snapshot
Coherency Traffic Reduction in Manycore Systems
inferred← citeshttps://doi.org/10.1109/embeddedcom-scalcom.2009.60openalex-snapshot
CMP Thread Assignment Based on Group Sharing L2 Cache
inferred← citeshttps://doi.org/10.1109/hipc.2009.5433215openalex-snapshot
Terascale chip multiprocessor memory hierarchy and programming model
inferred← citeshttps://doi.org/10.1109/hpca.2007.346180openalex-snapshot
An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/hpca.2008.4658652openalex-snapshot
An OS-based alternative to full hardware coherence on tiled CMPs
inferred← citeshttps://doi.org/10.1109/hpca.2009.4798236openalex-snapshot
Adaptive Spill-Receive for robust high-performance caching in CMPs
inferred← citeshttps://doi.org/10.1109/hpca.2011.5749731openalex-snapshot
CloudCache: Expanding and shrinking private caches
inferred← citeshttps://doi.org/10.1109/hpca.2011.5749732openalex-snapshot
MorphCache: A Reconfigurable Adaptive Multi-level Cache hierarchy
inferred← citeshttps://doi.org/10.1109/hpca.2011.5749733openalex-snapshot
NUcache: An efficient multicore cache organization based on Next-Use distance
inferred← citeshttps://doi.org/10.1109/hpca.2012.6169034openalex-snapshot
AgileRegulator: A hybrid voltage regulator scheme redeeming dark silicon for power efficiency in a multicore architecture
inferred← citeshttps://doi.org/10.1109/hpca.2014.6835975openalex-snapshot
Undersubscribed threading on clustered cache architectures
inferred← citeshttps://doi.org/10.1109/hpca.2015.7056061openalex-snapshot
Scaling distributed cache hierarchies through computation and data co-scheduling
inferred← citeshttps://doi.org/10.1109/hpca.2017.25openalex-snapshot
A Split Cache Hierarchy for Enabling Data-Oriented Optimizations
inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00047openalex-snapshot
Analyzing and Leveraging Decoupled L1 Caches in GPUs
inferred← citeshttps://doi.org/10.1109/hpca68181.2026.11408623openalex-snapshot
Enterprise Class On-Chip Accelerator Integration
inferred← citeshttps://doi.org/10.1109/hpcc.2008.13openalex-snapshot
A Novel Scheme to Balance the Cache Sharing in High Performance Computing System
inferred← citeshttps://doi.org/10.1109/iccd.2008.4751936openalex-snapshot
Ring data location prediction scheme for Non-Uniform Cache Architectures
inferred← citeshttps://doi.org/10.1109/iccd.2009.5413143openalex-snapshot
Avoiding cache thrashing due to private data placement in last-level cache for manycore scaling
inferred← citeshttps://doi.org/10.1109/iccrd.2011.5763907openalex-snapshot
Private cache partitioning: A method to reduce the off-chip missrate of concurrently executing applications in Chip-Multiprocessors
inferred← citeshttps://doi.org/10.1109/icis.2007.172openalex-snapshot
Split Private and Shared L2 Cache Architecture for Snooping-based CMP
inferred← citeshttps://doi.org/10.1109/icpads.2007.4447764openalex-snapshot
Comparative evaluation of multi-core cache occupancy strategies
inferred← citeshttps://doi.org/10.1109/icpads.2011.119openalex-snapshot
Set Utilization Based Dynamic Shared Cache Partitioning
inferred← citeshttps://doi.org/10.1109/icpp.2008.29openalex-snapshot
Taming Single-Thread Program Performance on Many Distributed On-Chip L2 Caches
inferred← citeshttps://doi.org/10.1109/iiswc.2007.4362180openalex-snapshot
An Evaluation of Server Consolidation Workloads for Multi-Core Designs
inferred← citeshttps://doi.org/10.1109/ipdps.2007.370584openalex-snapshot
Experimental Evaluation of Emerging Multi-core Architectures
inferred← citeshttps://doi.org/10.1109/ipdps.2013.75openalex-snapshot
RAIR: Interference Reduction in Regionalized Networks-on-Chip
inferred← citeshttps://doi.org/10.1109/iscas56072.2025.11044103openalex-snapshot
RRR: Robust runtime reconfigurable shared cache management scheme for GPGPUs
inferred← citeshttps://doi.org/10.1109/iscsct.2008.182openalex-snapshot
The Refresh Efficiency on Difference Processor Cache Architecture
inferred← citeshttps://doi.org/10.1109/ispa.2008.72openalex-snapshot
Adapting the Hyper-Ring Interconnect for Many-Core Processors
inferred← citeshttps://doi.org/10.1109/ispass.2007.363743openalex-snapshot
Modeling and Single-Pass Simulation of CMP Cache Capacity and Accessibility
inferred← citeshttps://doi.org/10.1109/ispaw.2011.25openalex-snapshot
Understanding How Non-uniform Distribution of Memory Accesses on Cache Sets Affects the System Performance of Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/l-ca.2007.6openalex-snapshot
Nahalal: Cache Organization for Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/l-ca.2010.7openalex-snapshot
A Dynamic Pressure-Aware Associative Placement Strategy for Large Scale Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/l-ca.2011.18openalex-snapshot
Experience with Improving Distributed Shared Cache Performance on Tilera's Tile Processor
inferred← citeshttps://doi.org/10.1109/micro.2010.41openalex-snapshot
Minimal Multi-threading: Finding and Removing Redundant Instructions in Multi-threaded Processors
inferred← citeshttps://doi.org/10.1109/micro50266.2020.00061openalex-snapshot
Jumanji: The Case for Dynamic NUCA in the Datacenter
inferred← citeshttps://doi.org/10.1109/micro50266.2020.00082openalex-snapshot
Selective Replication in Memory-Side GPU Caches
inferred← citeshttps://doi.org/10.1109/mm.2022.3193642openalex-snapshot
Enterprise-Class Multilevel Cache Design: Low Latency, Huge Capacity, and High Reliability
inferred← citeshttps://doi.org/10.1109/nas.2012.27openalex-snapshot
PSA-NUCA: A Pressure Self-Adapting Dynamic Non-uniform Cache Architecture
inferred← citeshttps://doi.org/10.1109/pact.2009.14openalex-snapshot
SOS: A Software-Oriented Distributed Shared Cache Management Approach for Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/pact.2009.24openalex-snapshot
DDCache: Decoupled and Delegable Cache Data and Metadata
inferred← citeshttps://doi.org/10.1109/pdcat.2011.36openalex-snapshot
Dynamic Thread Partition Algorithm Based on Sharing Data on CMP
inferred← citeshttps://doi.org/10.1109/rtas.2008.6openalex-snapshot
WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches
inferred← citeshttps://doi.org/10.1109/rtcsa.2007.16openalex-snapshot
Achieving Predictable Performance with On-Chip Shared L2 Caches for Manycore-Based Real-Time Systems
inferred← citeshttps://doi.org/10.1109/rtcsa.2010.49openalex-snapshot
Time-Predictable L2 Cache Design for High-Performance Real-Time Systems
inferred← citeshttps://doi.org/10.1109/sbac-pad.2009.12openalex-snapshot
Analysis of Performance Dependencies in NUCA-Based CMP Systems
inferred← citeshttps://doi.org/10.1109/sc.2010.50openalex-snapshot
Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support
inferred← citeshttps://doi.org/10.1109/sc.2010.54openalex-snapshot
The Sharing Tracker: Using Ideas from Cache Coherence Hardware to Reduce Off-Chip Memory Traffic with Non-Coherent Caches
inferred← citeshttps://doi.org/10.1109/tc.2009.138openalex-snapshot
PERFECTORY: A Fault-Tolerant Directory Memory Architecture
inferred← citeshttps://doi.org/10.1109/tc.2013.161openalex-snapshot
A Practical Data Classification Framework for Scalable and High Performance Chip-Multiprocessors
inferred← citeshttps://doi.org/10.1109/tc.2013.44openalex-snapshot
A Cache Tuning Heuristic for Multicore Architectures
inferred← citeshttps://doi.org/10.1109/tpds.2007.1091openalex-snapshot
A NUCA Substrate for Flexible CMP Cache Sharing
inferred← citeshttps://doi.org/10.1109/tpds.2009.31openalex-snapshot
Modeling and Stack Simulation of CMP Cache Capacity and Accessibility
inferred← citeshttps://doi.org/10.1109/tpds.2011.200openalex-snapshot
Distributed Cooperative Caching: An Energy Efficient Memory Scheme for Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/tpds.2011.214openalex-snapshot
High-Performance Energy-Efficient Multicore Embedded Computing
inferred← citeshttps://doi.org/10.1109/tpds.2011.238openalex-snapshot
Codesign of NoC and Cache Organization for Reducing Access Latency in Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/tpds.2017.2657512openalex-snapshot
Dynamic Associativity Management in Tiled CMPs by Runtime Adaptation of Fellow Sets
inferred← citeshttps://doi.org/10.1109/tvlsi.2012.2220791openalex-snapshot
Exploiting Replicated Cache Blocks to Reduce L2 Cache Leakage in CMPs
inferred← citeshttps://doi.org/10.1145/1150019.1136509openalex-snapshot
Cooperative Caching for Chip Multiprocessors
inferred← citeshttps://doi.org/10.1145/1178597.1178613openalex-snapshot
A flexible data to L2 cache mapping approach for future multicore processors
inferred← citeshttps://doi.org/10.1145/1241601.1241607openalex-snapshot
CMP cache performance projection
inferred← citeshttps://doi.org/10.1145/1248377.1248398openalex-snapshot
Proximity-aware directory-based coherence for multi-core processor architectures
inferred← citeshttps://doi.org/10.1145/1250662.1250670openalex-snapshot
Virtual hierarchies to support server consolidation
inferred← citeshttps://doi.org/10.1145/1250662.1250708openalex-snapshot
Interconnect design considerations for large NUCA caches
inferred← citeshttps://doi.org/10.1145/1273440.1250670openalex-snapshot
Virtual hierarchies to support server consolidation
inferred← citeshttps://doi.org/10.1145/1273440.1250708openalex-snapshot
Interconnect design considerations for large NUCA caches
inferred← citeshttps://doi.org/10.1145/1274971.1275005openalex-snapshot
Cooperative cache partitioning for chip multiprocessors
inferred← citeshttps://doi.org/10.1145/1283780.1283793openalex-snapshot
A reusability-aware cache memory sharing technique for high-performance low-power CMPs with private L2 caches
inferred← citeshttps://doi.org/10.1145/1378533.1378535openalex-snapshot
Utilizing shared data in chip multiprocessors with the Nahalal architecture
inferred← citeshttps://doi.org/10.1145/1378533.1378536openalex-snapshot
A consistency architecture for hierarchical shared caches
inferred← citeshttps://doi.org/10.1145/1399972.1399982openalex-snapshot
Towards hybrid last level caches for chip-multiprocessors
inferred← citeshttps://doi.org/10.1145/1454115.1454136openalex-snapshot
Distributed cooperative caching
inferred← citeshttps://doi.org/10.1145/1454115.1454138openalex-snapshot
Improving support for locality and fine-grain sharing in chip multiprocessors
inferred← citeshttps://doi.org/10.1145/1454115.1454144openalex-snapshot
Leveraging on-chip networks for data cache migration in chip multiprocessors
inferred← citeshttps://doi.org/10.1145/1509084.1509089openalex-snapshot
A leakage-aware cache sharing technique for low-power chip multi-processors (CMPs) with private L2 caches
inferred← citeshttps://doi.org/10.1145/1542275.1542289openalex-snapshot
Dynamic cache clustering for chip multiprocessors
inferred← citeshttps://doi.org/10.1145/1542452.1542464openalex-snapshot
Push-assisted migration of real-time tasks in multi-core processors
inferred← citeshttps://doi.org/10.1145/1543136.1542464openalex-snapshot
Push-assisted migration of real-time tasks in multi-core processors
inferred← citeshttps://doi.org/10.1145/1736065.1736069openalex-snapshot
An analysis of on-chip interconnection networks for large-scale chip multiprocessors
inferred← citeshttps://doi.org/10.1145/1739025.1739030openalex-snapshot
Compiler-based data classification for hybrid caching
inferred← citeshttps://doi.org/10.1145/1785481.1785552openalex-snapshot
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
inferred← citeshttps://doi.org/10.1145/1806596.1806605openalex-snapshot
Cache topology aware computation mapping for multicores
inferred← citeshttps://doi.org/10.1145/1809028.1806605openalex-snapshot
Cache topology aware computation mapping for multicores
inferred← citeshttps://doi.org/10.1145/1840845.1840874openalex-snapshot
Replication-aware leakage management in chip multiprocessors with private L2 cache
inferred← citeshttps://doi.org/10.1145/1854273.1854314openalex-snapshot
Handling the problems and opportunities posed by multiple on-chip memory controllers
inferred← citeshttps://doi.org/10.1145/1854273.1854354openalex-snapshot
NoC-aware cache design for chip multiprocessors
inferred← citeshttps://doi.org/10.1145/1944862.1944891openalex-snapshot
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
inferred← citeshttps://doi.org/10.1145/1950365.1950411openalex-snapshot
Inter-core prefetching for multicore processors using migrating helper threads
inferred← citeshttps://doi.org/10.1145/1961295.1950411openalex-snapshot
Inter-core prefetching for multicore processors using migrating helper threads
inferred← citeshttps://doi.org/10.1145/1961296.1950411openalex-snapshot
Inter-core prefetching for multicore processors using migrating helper threads
inferred← citeshttps://doi.org/10.1145/1973009.1973028openalex-snapshot
Design and management of 3D-stacked NUCA cache for chip multiprocessors
inferred← citeshttps://doi.org/10.1145/2019608.2019614openalex-snapshot
Evaluating placement policies for managing capacity sharing in CMP architectures with private caches
inferred← citeshttps://doi.org/10.1145/2086696.2086723openalex-snapshot
The gradient-based cache partitioning algorithm
inferred← citeshttps://doi.org/10.1145/2103380.2103385openalex-snapshot
Throttling capacity sharing in private L2 caches of CMPs
inferred← citeshttps://doi.org/10.1145/2377978.2377979openalex-snapshot
A collaborative memory system for high-performance and cost-effective clustered architectures
inferred← citeshttps://doi.org/10.1145/2480741.2480749openalex-snapshot
A survey on cache tuning from a power/energy perspective
inferred← citeshttps://doi.org/10.1145/2541940.2541976openalex-snapshot
Locality-oblivious cache organization leveraging single-cycle multi-hop NoCs
inferred← citeshttps://doi.org/10.1145/2566568openalex-snapshot
Exploiting replication to improve performances of NUCA-based CMP systems
inferred← citeshttps://doi.org/10.1145/2644865.2541976openalex-snapshot
Locality-oblivious cache organization leveraging single-cycle multi-hop NoCs
inferred← citeshttps://doi.org/10.1145/2654822.2541976openalex-snapshot
Locality-oblivious cache organization leveraging single-cycle multi-hop NoCs
inferred← citeshttps://doi.org/10.1145/2695664.2695783openalex-snapshot
Dynamic associativity management using utility based way-sharing
inferred← citeshttps://doi.org/10.1145/2723772.2723779openalex-snapshot
Cycle-based Model to Evaluate Consistency Protocols within a Multi-protocol Compilation Tool-chain
inferred← citeshttps://doi.org/10.1145/2807591.2807649openalex-snapshot
Automatic sharing classification and timely push for cache-coherent systems
inferred← citeshttps://doi.org/10.1145/2907946openalex-snapshot
A Framework for Block Placement, Migration, and Fast Searching in Tiled-DNUCA Architecture
inferred← citeshttps://doi.org/10.1145/3062394openalex-snapshot
A Survey of Techniques for Cache Partitioning in Multicore Processors
inferred← citeshttps://doi.org/10.1145/3149356openalex-snapshot
Experience from Two Years of Visualizing Flash with SSDPlayer
inferred← citeshttps://doi.org/10.1145/3307650.3322235openalex-snapshot
Adaptive memory-side last-level GPU caching
inferred← citeshttps://doi.org/10.1145/3695053.3731061openalex-snapshot
NUPEA: Optimizing Critical Loads on Spatial Dataflow Architectures via Non-Uniform Processing-Element Access
inferred← citeshttps://doi.org/10.1184/r1/6468944openalex-snapshot
Investigating the Viability of Bufferless NoCs in Modern Chip Multi-processor Systems
inferred← citeshttps://doi.org/10.15308/sinteza-2023-159-165openalex-snapshot
Scratchpad Memory Unit in Hybrid Control-flow and Dataflow Architectures
inferred← citeshttps://doi.org/10.15623/ijret.2013.0214009openalex-snapshot
CMP CACHE ARCHITECTURES - A SURVEY
inferred← citeshttps://doi.org/10.2200/s00683ed1v01y201511cac036openalex-snapshot
A Primer on Compression in the Memory Hierarchy
inferred← citeshttps://doi.org/10.4028/www.scientific.net/amm.198-199.523openalex-snapshot
Static Analysis of Run-Time Inter-Core Interferences for Concurrent Programs in Shared Cache Multicore Architectures
inferred← citeshttps://doi.org/10.4995/thesis/10251/165254openalex-snapshot
Novel Cache Hierarchies with Photonic Interconnects for Chip Multiprocessors
inferred← citeshttps://doi.org/10.5120/1131-1482openalex-snapshot
Adaptive Zone-Aware Multi-bank on Chip last level L2 Cache Partitioning for Chip Multiprocessors
inferred← citeshttps://doi.org/10.5555/1413370.1413399openalex-snapshot
A novel migration-based NUCA design for chip multiprocessors
inferred← citeshttps://doi.org/10.5555/1874620.1874807openalex-snapshot
Group-caching for NoC based multicore cache coherent systems
inferred← citeshttps://doi.org/10.5626/jcse.2011.5.2.131openalex-snapshot
An Interference Matrix Based Approach to Bounding Worst-Case Inter-Thread Cache Interferences and WCET for Multi-Core Processors
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