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Two‐phase trace‐driven simulation (TPTS): a fast multicore processor architecture simulation approach

https://doi.org/10.1002/spe.956
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1017/cbo9780511612398openalex-snapshot
Measuring Computer Performance
inferredcites →https://doi.org/10.1109/2.982916openalex-snapshot
Simics: A full system simulation platform
inferredcites →https://doi.org/10.1109/2.982917openalex-snapshot
SimpleScalar: an infrastructure for computer system modeling
inferredcites →https://doi.org/10.1109/4434.895100openalex-snapshot
Wisconsin Wind Tunnel II: a fast, portable parallel architecture simulator
inferredcites →https://doi.org/10.1109/hpca.2006.1598110openalex-snapshot
Exploiting Parallelism and Structure to Accelerate the Simulation of Chip Multi-processors
inferredcites →https://doi.org/10.1109/hpca.2007.346179openalex-snapshot
Interconnect-Centric Computing
inferredcites →https://doi.org/10.1109/iccd.1996.563596openalex-snapshot
Can trace-driven simulators accurately predict superscalar performance?
inferredcites →https://doi.org/10.1109/isca.1998.694761openalex-snapshot
An analysis of database workload performance on simultaneous multithreaded processors
inferredcites →https://doi.org/10.1109/isca.2004.1310786openalex-snapshot
A first-order superscalar processor model
inferredcites →https://doi.org/10.1109/isca.2006.17openalex-snapshot
Cooperative Caching for Chip Multiprocessors
inferredcites →https://doi.org/10.1109/ispass.2005.1430560openalex-snapshot
Accelerating Multiprocessor Simulation with a Memory Timestamp Record
inferredcites →https://doi.org/10.1109/ispass.2005.1430562openalex-snapshot
Enhancing Multiprocessor Architecture Simulation Speed Using Matched-Pair Comparison
inferredcites →https://doi.org/10.1109/ispass.2006.1620785openalex-snapshot
Simulation sampling with live-points
inferredcites →https://doi.org/10.1109/ispass.2007.363730openalex-snapshot
Performance Modeling and Analysis for AMD's High Performance Microprocessors
inferredcites →https://doi.org/10.1109/ispass.2008.4510735openalex-snapshot
An Adaptive Synchronization Technique for Parallel Simulation of Networked Clusters
inferredcites →https://doi.org/10.1109/ispass.2009.4919655openalex-snapshot
Accurately approximating superscalar processor performance from traces
inferredcites →https://doi.org/10.1109/isscc.2007.373606openalex-snapshot
An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS
inferredcites →https://doi.org/10.1109/mascot.1994.284422openalex-snapshot
MINT: a front end for efficient simulation of shared-memory multiprocessors
inferredcites →https://doi.org/10.1109/mc.2006.404openalex-snapshot
The future of simulation: a field of dreams
inferredcites →https://doi.org/10.1109/micro.2006.24openalex-snapshot
Fair Queuing Memory Systems
inferredcites →https://doi.org/10.1109/micro.2006.31openalex-snapshot
Managing Distributed, Shared L2 Caches through OS-Level Page Allocation
inferredcites →https://doi.org/10.1109/micro.2007.17openalex-snapshot
A Framework for Providing Quality of Service in Chip Multi-Processors
inferredcites →https://doi.org/10.1109/micro.2007.36openalex-snapshot
FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators
inferredcites →https://doi.org/10.1109/micro.2007.6openalex-snapshot
Organizing Committee
inferredcites →https://doi.org/10.1109/mm.2005.35openalex-snapshot
Niagara: A 32-Way Multithreaded Sparc Processor
inferredcites →https://doi.org/10.1109/mm.2008.39openalex-snapshot
Guest Editors' Introduction: Interaction of Many-Core Computer Architecture and Operating Systems
inferredcites →https://doi.org/10.1145/1006209.1006246openalex-snapshot
CQoS
inferredcites →https://doi.org/10.1145/1028176.1006729openalex-snapshot
A First-Order Superscalar Processor Model
inferredcites →https://doi.org/10.1145/1080695.1069998openalex-snapshot
Victim Replication
inferredcites →https://doi.org/10.1145/1105734.1105747openalex-snapshot
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
inferredcites →https://doi.org/10.1145/1150019.1136509openalex-snapshot
Cooperative Caching for Chip Multiprocessors
inferredcites →https://doi.org/10.1145/1344671.1344684openalex-snapshot
A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs
inferredcites →https://doi.org/10.1145/1577129.1577133openalex-snapshot
How to simulate 1000 cores
inferredcites →https://doi.org/10.1145/1577129.1577134openalex-snapshot
SlackSim
inferredcites →https://doi.org/10.1145/166955.166977openalex-snapshot
Cache inclusion and processor sampling in multiprocessor simulations
inferredcites →https://doi.org/10.1145/166962.166977openalex-snapshot
Cache inclusion and processor sampling in multiprocessor simulations
inferredcites →https://doi.org/10.1145/223982.223990openalex-snapshot
The SPLASH-2 programs
inferredcites →https://doi.org/10.1145/254180.254184openalex-snapshot
Trace-driven memory simulation
inferredcites →https://doi.org/10.1145/277651.277672openalex-snapshot
Lamport clocks
inferredcites →https://doi.org/10.1145/279358.279367openalex-snapshot
An analysis of database workload performance on simultaneous multithreaded processors
inferredcites →https://doi.org/10.1145/605397.605403openalex-snapshot
Automatically characterizing large scale program behavior
inferredcites →https://doi.org/10.1145/643114.643116openalex-snapshot
Parallel simulation of chip-multiprocessor architectures
inferredcites →https://doi.org/10.1145/778553.778554openalex-snapshot
Flexible reference trace reduction for VM simulations
inferredcites →https://doi.org/10.1145/859618.859629openalex-snapshot
SMARTS
inferredcites →https://doi.org/10.1145/98457.98497openalex-snapshot
Efficient trace-driven simulation method for cache performance analysis
inferredcites →https://doi.org/10.1145/98457.98503openalex-snapshot
Blocking: exploiting spatial locality for trace compaction
inferredcites →https://doi.org/10.1145/98460.98497openalex-snapshot
Efficient trace-driven simulation method for cache performance analysis
inferredcites →https://doi.org/10.1145/98460.98503openalex-snapshot
Blocking: exploiting spatial locality for trace compaction
inferredcites →https://doi.org/10.5555/1025127.1026001openalex-snapshot
Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture
inferredcites →https://doi.org/10.5555/1331699.1331723openalex-snapshot
FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-030-41050-6_12openalex-snapshot
Evaluating Cache Line Behavior Predictors for Energy Efficient Processors
inferred← citeshttps://doi.org/10.1016/j.jpdc.2012.12.002openalex-snapshot
Accurately modeling superscalar processor performance with reduced trace
inferred← citeshttps://doi.org/10.1109/hpca.2011.5749731openalex-snapshot
CloudCache: Expanding and shrinking private caches
inferred← citeshttps://doi.org/10.1109/hpcsim.2015.7237110openalex-snapshot
Current challenges in simulations of HPC systems
inferred← citeshttps://doi.org/10.1109/ispass.2013.6557160openalex-snapshot
Trace filtering of multithreaded applications for CMP memory simulation
inferred← citeshttps://doi.org/10.1109/samos.2016.7818336openalex-snapshot
Exploring system performance using elastic traces: Fast, accurate and portable
inferred← citeshttps://doi.org/10.1109/sbesc.2018.00046openalex-snapshot
Evaluating Dead Line Predictors Efficiency with Drowsy Technique
inferred← citeshttps://doi.org/10.1109/vlsisoc.2011.6081615openalex-snapshot
Context-aware compiled simulation of out-of-order processor behavior based on atomic traces
inferred← citeshttps://doi.org/10.1109/wscad.2018.00047openalex-snapshot
Introducing Drowsy Technique to Cache Line Usage Predictors
inferred← citeshttps://doi.org/10.1145/2086696.2086715openalex-snapshot
On the simulation of large-scale architectures using multiple application abstraction levels
inferred← citeshttps://doi.org/10.1145/2480741.2480749openalex-snapshot
A survey on cache tuning from a power/energy perspective
inferred← citeshttps://doi.org/10.15514/ispras-2019-31(3)-4openalex-snapshot
An Exploration of Approaches to Instruction Pipeline Implementation for Cycle-Accurate Simulators of «Elbrus»
inferred← citeshttps://doi.org/10.2316/journal.205.2012.1.205-5600openalex-snapshot
A LOCALIZED PARALLEL TRACE I/O METHOD FOR TRACE-DRIVEN SIMULATOR
inferred← citeshttps://doi.org/10.5821/dissertation-2117-95244openalex-snapshot
Raising the level of abstraction : simulation of large chip multiprocessors running multithreaded applications
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