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Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot
Networks on chips: a new SoC paradigm
inferredcites →https://doi.org/10.1109/2.982916openalex-snapshot
Simics: A full system simulation platform
inferredcites →https://doi.org/10.1109/asic.2001.954688openalex-snapshot
A stochastic global net-length distribution for a three-dimensional system-on-a-chip (3D-SoC)
inferredcites →https://doi.org/10.1109/aspdac.2004.1337617openalex-snapshot
2.5D system integration: a design driven system implementation schema
inferredcites →https://doi.org/10.1109/cicc.2003.1249391openalex-snapshot
Three dimensional CMOS devices and integrated circuits
inferredcites →https://doi.org/10.1109/hpca.2001.903268openalex-snapshot
A delay model and speculative architecture for pipelined routers
inferredcites →https://doi.org/10.1109/iccad.2004.1382522openalex-snapshot
Problems or opportunities? Beyond the 90nm frontier [Keynote]
inferredcites →https://doi.org/10.1109/iccd.2004.1347939openalex-snapshot
3D processing technology and its impact on iA32 microprocessors
inferredcites →https://doi.org/10.1109/iccd.2005.108openalex-snapshot
Three-dimensional cache design exploration using 3DCacti
inferredcites →https://doi.org/10.1109/iccd.2005.65openalex-snapshot
Implementing caches in a 3D technology for high performance processors
inferredcites →https://doi.org/10.1109/isca.2000.854395openalex-snapshot
Clock rate versus IPC: the end of the road for conventional microarchitectures
inferredcites →https://doi.org/10.1109/isca.2004.1310774openalex-snapshot
Low-latency virtual-channel routers for on-chip networks
inferredcites →https://doi.org/10.1109/isca.2005.53openalex-snapshot
Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors
inferredcites →https://doi.org/10.1109/mdt.2005.136openalex-snapshot
Demystifying 3D ICs: The Pros and Cons of Going Vertical
inferredcites →https://doi.org/10.1109/mdt.2005.138openalex-snapshot
First-Order Performance Prediction of Cache Memory with Wafer-Level3D Integration
inferredcites →https://doi.org/10.1109/micro.2002.1176258openalex-snapshot
Orion: a power-performance simulator for interconnection networks
inferredcites →https://doi.org/10.1109/micro.2003.1253183openalex-snapshot
Distance associativity for high-performance energy-efficient non-uniform cache architectures
inferredcites →https://doi.org/10.1109/micro.2004.21openalex-snapshot
Managing Wire Delay in Large Chip-Multiprocessor Caches
inferredcites →https://doi.org/10.1109/mm.2005.35openalex-snapshot
Niagara: A 32-Way Multithreaded Sparc Processor
inferredcites →https://doi.org/10.1109/tcad.2005.844106openalex-snapshot
Energy- and performance-aware mapping for regular NoC architectures
inferredcites →https://doi.org/10.1109/vlsid.2006.10openalex-snapshot
A hybrid SoC interconnect with dynamic TDMA-based transaction-less buses and on-chip networks
inferredcites →https://doi.org/10.1109/vlsit.2004.1345495openalex-snapshot
The revolutionary and truly 3-dimensional 25F/sup 2/ SRAM technology with the smallest S/sup 3/ ( stacked single-crystal Si) cell, 0.16um/sup 2/, and SSTFT (atacked single-crystal thin film transistor) for ultra high density SRAM
inferredcites →https://doi.org/10.1145/1080695.1070001openalex-snapshot
Optimizing Replication, Communication, and Capacity Allocation in CMPs
inferredcites →https://doi.org/10.1145/1088149.1088154openalex-snapshot
A NUCA substrate for flexible CMP cache sharing
inferredcites →https://doi.org/10.1145/1095890.1095915openalex-snapshot
Design and analysis of an NoC architecture from performance, reliability and energy perspective
inferredcites →https://doi.org/10.1145/1120725.1120787openalex-snapshot
Thermal-driven multilevel routing for 3-D ICs
inferredcites →https://doi.org/10.1145/237090.237140openalex-snapshot
The case for a single-chip multiprocessor
inferredcites →https://doi.org/10.1145/605397.605420openalex-snapshot
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
inferredcites →https://doi.org/10.1145/981066.981091openalex-snapshot
Technology, performance, and computer-aided design of three-dimensional integrated circuits
inferredcites →https://doi.org/10.1147/rd.494.0589openalex-snapshot
Introduction to the Cell multiprocessor
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/spe.1150openalex-snapshot
An asynchronous hierarchical router for networks‐on‐chip‐based three‐dimensional multi‐processor system‐on‐chip
inferred← citeshttps://doi.org/10.1007/978-981-32-9767-8_27openalex-snapshot
2L-2D Routing for Buffered Mesh Network-on-Chip
inferred← citeshttps://doi.org/10.1016/j.vlsi.2017.12.002openalex-snapshot
Analyzing power-thermal-performance trade-offs in a high-performance 3D NoC architecture
inferred← citeshttps://doi.org/10.1109/dsd.2011.26openalex-snapshot
LastZ: An Ultra Optimized 3D Networks-on-Chip Architecture
inferred← citeshttps://doi.org/10.1109/dsd.2012.9openalex-snapshot
A Methodology for Early Exploration of TSV Placement Topologies in 3D Stacked ICs
inferred← citeshttps://doi.org/10.1109/hpca.2012.6169037openalex-snapshot
Dynamically heterogeneous cores through 3D resource pooling
inferred← citeshttps://doi.org/10.1109/hpcc.2012.222openalex-snapshot
Area Utilization Based Mapping for Network-on-chip Architectures with Over-sized IP Cores
inferred← citeshttps://doi.org/10.1109/iccad.2015.7372639openalex-snapshot
Optimizing 3D NoC design for energy efficiency: A machine learning approach
inferred← citeshttps://doi.org/10.1109/icspc46172.2019.8976501openalex-snapshot
State of art of Network on Chip
inferred← citeshttps://doi.org/10.1109/iraniancee.2013.6599754openalex-snapshot
An efficient implementation of Hamiltonian path based multicast routing for 3D interconnection networks
inferred← citeshttps://doi.org/10.1109/isvlsi.2007.79openalex-snapshot
Performance Evaluation for Three-Dimensional Networks-On-Chip
inferred← citeshttps://doi.org/10.1109/mm.2007.59openalex-snapshot
Processor Design in 3D Die-Stacking Technologies
inferred← citeshttps://doi.org/10.1109/pdp.2012.70openalex-snapshot
An Efficient Hybridization Scheme for Stacked Mesh 3D NoC Architecture
inferred← citeshttps://doi.org/10.1109/pdp.2013.50openalex-snapshot
Enhancing Performance of 3D Interconnection Networks using Efficient Multicast Communication Protocol
inferred← citeshttps://doi.org/10.1109/tc.2008.142openalex-snapshot
Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation
inferred← citeshttps://doi.org/10.1109/tc.2009.92openalex-snapshot
3D-Integrated SRAM Components for High-Performance Microprocessors
inferred← citeshttps://doi.org/10.1109/tc.2011.239openalex-snapshot
Elevator-First: A Deadlock-Free Distributed Routing Algorithm for Vertically Partially Connected 3D-NoCs
inferred← citeshttps://doi.org/10.1109/tc.2012.129openalex-snapshot
Process Variation-Aware Nonuniform Cache Management in a 3D Die-Stacked Multicore Processor
inferred← citeshttps://doi.org/10.1109/tc.2012.249openalex-snapshot
3D NoC with Inductive-Coupling Links for Building-Block SiPs
inferred← citeshttps://doi.org/10.1109/tc.2012.255openalex-snapshot
Path-Based Partitioning Methods for 3D Networks-on-Chip with Minimal Adaptive Routing
inferred← citeshttps://doi.org/10.1109/tpds.2008.233openalex-snapshot
Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network
inferred← citeshttps://doi.org/10.1145/1250662.1250680openalex-snapshot
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
inferred← citeshttps://doi.org/10.1145/1250662.1250708openalex-snapshot
Interconnect design considerations for large NUCA caches
inferred← citeshttps://doi.org/10.1145/1273440.1250680openalex-snapshot
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
inferred← citeshttps://doi.org/10.1145/1273440.1250708openalex-snapshot
Interconnect design considerations for large NUCA caches
inferred← citeshttps://doi.org/10.1145/1366230.1366261openalex-snapshot
A modular 3d processor for flexible product design and technology migration
inferred← citeshttps://doi.org/10.1145/1375457.1375498openalex-snapshot
Software-directed combined cpu/link voltage scaling fornoc-based cmps
inferred← citeshttps://doi.org/10.1145/1384529.1375498openalex-snapshot
Software-directed combined cpu/link voltage scaling fornoc-based cmps
inferred← citeshttps://doi.org/10.1145/1391469.1391585openalex-snapshot
A practical approach of memory access parallelization to exploit multiple off-chip DDR memories
inferred← citeshttps://doi.org/10.1145/1394608.1382127openalex-snapshot
A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies
inferred← citeshttps://doi.org/10.1145/1403375.1403677openalex-snapshot
An open-loop flow control scheme based on the accurate global information of on-chip communication
inferred← citeshttps://doi.org/10.1145/1412587.1412590openalex-snapshot
Investigating the effects of fine-grain three-dimensional integration on microarchitecture design
inferred← citeshttps://doi.org/10.1145/1412587.1412592openalex-snapshot
Parametric yield management for 3D ICs
inferred← citeshttps://doi.org/10.1145/1555754.1555761openalex-snapshot
Hybrid cache architecture with disparate memory technologies
inferred← citeshttps://doi.org/10.1145/1555815.1555761openalex-snapshot
Hybrid cache architecture with disparate memory technologies
inferred← citeshttps://doi.org/10.1145/1594233.1594306openalex-snapshot
Exploration of 3D stacked L2 cache design for high performance and efficient thermal control
inferred← citeshttps://doi.org/10.1145/1629911.1630061openalex-snapshot
Exploring serial vertical interconnects for 3D ICs
inferred← citeshttps://doi.org/10.1145/1629911.1630117openalex-snapshot
An SDRAM-aware router for Networks-on-Chip
inferred← citeshttps://doi.org/10.1145/1669112.1669139openalex-snapshot
Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy
inferred← citeshttps://doi.org/10.1145/1669112.1669141openalex-snapshot
Variation-tolerant non-uniform 3D cache management in die stacked multicore processor
inferred← citeshttps://doi.org/10.1145/1687399.1687447openalex-snapshot
Thermal modeling for 3D-ICs with integrated microchannel cooling
inferred← citeshttps://doi.org/10.1145/1880037.1880040openalex-snapshot
Design exploration of hybrid caches with disparate memory technologies
inferred← citeshttps://doi.org/10.1145/1882486.1882517openalex-snapshot
A novel 3D layer-multiplexed on-chip network
inferred← citeshttps://doi.org/10.1145/1999946.1999955openalex-snapshot
A vertical bubble flow network using inductive-coupling for 3-D CMPs
inferred← citeshttps://doi.org/10.1145/1999946.1999957openalex-snapshot
Congestion aware, fault tolerant, and thermally efficient inter-layer communication scheme for hybrid NoC-bus 3D architectures
inferred← citeshttps://doi.org/10.1145/1999946.1999958openalex-snapshot
Exploring partitioning methods for 3D Networks-on-Chip utilizing adaptive routing model
inferred← citeshttps://doi.org/10.1145/2016604.2016621openalex-snapshot
Cluster-based topologies for 3D stacked architectures
inferred← citeshttps://doi.org/10.1145/2155620.2155677openalex-snapshot
A data layout optimization framework for NUCA-based multicores
inferred← citeshttps://doi.org/10.1145/2159542.2159544openalex-snapshot
Optimized 3D Network-on-Chip Design Using Simulated Allocation
inferred← citeshttps://doi.org/10.1145/2159542.2159545openalex-snapshot
Performance/Thermal-Aware Design of 3D-Stacked L2 Caches for CMPs
inferred← citeshttps://doi.org/10.1145/2228360.2228427openalex-snapshot
Cost-efficient buffer sizing in shared-memory 3D-MPSoCs using wide I/O interfaces
inferred← citeshttps://doi.org/10.1145/2236576.2236579openalex-snapshot
Exploration of heuristic scheduling algorithms for 3D multicore processors
inferred← citeshttps://doi.org/10.1145/2401716.2401725openalex-snapshot
A high-efficiency low-cost heterogeneous 3D network-on-chip design
inferred← citeshttps://doi.org/10.1145/2429384.2429538openalex-snapshot
Multiobjective optimization of deadspace, a critical resource for 3D-IC integration
inferred← citeshttps://doi.org/10.1145/2451916.2451921openalex-snapshot
Utilizing 2D and 3D rectilinear blocks for efficient IP reuse and floorplanning of 3D-integrated systems
inferred← citeshttps://doi.org/10.1145/2699832openalex-snapshot
Yield Improvement for 3D Wafer-to-Wafer Stacked ICs Using Wafer Matching
inferred← citeshttps://doi.org/10.1145/2818950.2818951openalex-snapshot
Interconnect-Memory Challenges for Multi-chip, Silicon Interposer Systems
inferred← citeshttps://doi.org/10.1145/2830772.2830808openalex-snapshot
Enabling interposer-based disintegration of multi-core processors
inferred← citeshttps://doi.org/10.1145/2835512.2835514openalex-snapshot
Design of TSV-Sharing Topologies for Cost-Effective 3D Networks-on-Chip
inferred← citeshttps://doi.org/10.1145/2907946openalex-snapshot
A Framework for Block Placement, Migration, and Fast Searching in Tiled-DNUCA Architecture
inferred← citeshttps://doi.org/10.1145/3130218.3130219openalex-snapshot
3D NoC-Enabled Heterogeneous Manycore Architectures for Accelerating CNN Training
inferred← citeshttps://doi.org/10.1145/3197567openalex-snapshot
Design Space Exploration of 3D Network-on-Chip
inferred← citeshttps://doi.org/10.1145/3631882.3631905openalex-snapshot
MC-ELMM: Multi-Chip Endurance-Limited Memory Management
inferred← citeshttps://doi.org/10.2200/s00365ed1v01y201105cac017openalex-snapshot
Multi-Core Cache Hierarchies
inferred← citeshttps://doi.org/10.2200/s00772ed1v01y201704cac040openalex-snapshot
On-Chip Networks, Second Edition
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