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LastZ: An Ultra Optimized 3D Networks-on-Chip Architecture
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1016/b978-0-12-374343-5.x1000-3openalex-snapshot
Three-dimensional Integrated Circuit Design
inferredcites →https://doi.org/10.1109/2.976921openalex-snapshot
Networks on chips: a new SoC paradigm
inferredcites →https://doi.org/10.1109/hpca.2009.4798234openalex-snapshot
A low-radix and low-diameter 3D interconnection network design
inferredcites →https://doi.org/10.1109/iccad.2005.1560164openalex-snapshot
Thermal via planning for 3-D ICs
inferredcites →https://doi.org/10.1109/iccd.2008.4751852openalex-snapshot
Near-optimal oblivious routing on three-dimensional mesh networks
inferredcites →https://doi.org/10.1109/icpp.2007.79openalex-snapshot
Tightly-Coupled Multi-Layer Topologies for 3-D NoCs
inferredcites →https://doi.org/10.1109/isca.2006.18openalex-snapshot
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
inferredcites →https://doi.org/10.1109/isca.2008.13openalex-snapshot
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
inferredcites →https://doi.org/10.1109/isvlsi.2010.21openalex-snapshot
BBVC-3D-NoC: An Efficient 3D NoC Architecture Using Bidirectional Bisynchronous Vertical Channels
inferredcites →https://doi.org/10.1109/jproc.2006.873612openalex-snapshot
Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs
inferredcites →https://doi.org/10.1109/les.2009.2034710openalex-snapshot
A Layer-Multiplexed 3D On-Chip Network Architecture
inferredcites →https://doi.org/10.1109/micro.2006.50openalex-snapshot
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers
inferredcites →https://doi.org/10.1109/mm.2007.59openalex-snapshot
Processor Design in 3D Die-Stacking Technologies
inferredcites →https://doi.org/10.1109/newcas.2010.5604033openalex-snapshot
Performance analysis and optimization for homogenous multi-core system based on 3D Torus Network on Chip
inferredcites →https://doi.org/10.1109/nocs.2009.5071456openalex-snapshot
Networks-on-chip in emerging interconnect paradigms: Advantages and challenges
inferredcites →https://doi.org/10.1109/norchip.2010.5669453openalex-snapshot
Research and practices on 3D networks-on-chip architectures
inferredcites →https://doi.org/10.1109/norchp.2009.5397851openalex-snapshot
A study of 3D Network-on-Chip design for data parallel H.264 coding
inferredcites →https://doi.org/10.1109/tc.2008.142openalex-snapshot
Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation
inferredcites →https://doi.org/10.1145/1150019.1136497openalex-snapshot
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
inferredcites →https://doi.org/10.1145/1250662.1250680openalex-snapshot
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
inferredcites →https://doi.org/10.1145/1999946.1999957openalex-snapshot
Congestion aware, fault tolerant, and thermally efficient inter-layer communication scheme for hybrid NoC-bus 3D architectures
inferredcites →https://doi.org/10.1145/605397.605420openalex-snapshot
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
inferredcites →https://doi.org/10.1145/635508.605420openalex-snapshot
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
inferredcites →https://doi.org/10.1147/rd.504.0491openalex-snapshot
Three-dimensional integrated circuits
inferredcites →https://doi.org/10.1166/jolpe.2009.1038openalex-snapshot
Forecasting-Based Dynamic Virtual Channel Management for Power Reduction in Network-on-Chips
inferredcites →https://doi.org/10.1166/jolpe.2009.1039openalex-snapshot
A Novel Synthetic Traffic Pattern for Power/Performance Analysis of Network-on-Chips Using Negative Exponential Distribution
inferredcites →https://doi.org/10.4028/www.scientific.net/amr.403-408.4009openalex-snapshot
Exploring DRAM Last Level Cache for 3D Network-on-Chip Architecture
inferredcites →https://doi.org/10.5555/1129601.1129707openalex-snapshot
Thermal via planning for 3-D ICs
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-030-16657-1_86openalex-snapshot
OP3DBFT: A Power and Performance Optimal 3D BFT NoC Architecture
inferred← citeshttps://doi.org/10.1016/j.meegid.2017.11.013openalex-snapshot
The dynamic evolution of Drosophila innubila Nudivirus
inferred← citeshttps://doi.org/10.1016/j.micpro.2013.04.013openalex-snapshot
Virtualized and fault-tolerant inter-layer-links for 3D-ICs
inferred← citeshttps://doi.org/10.1016/j.simpat.2019.101929openalex-snapshot
Extending BookSim2.0 and HotSpot6.0 for power, performance and thermal evaluation of 3D NoC architectures
inferred← citeshttps://doi.org/10.1016/j.sysarc.2013.03.005openalex-snapshot
Deadlock-free generic routing algorithms for 3-dimensional Networks-on-Chip with reduced vertical link density topologies
inferred← citeshttps://doi.org/10.1073/pnas.2423818122openalex-snapshot
Symbiosis with and mimicry of corals were facilitated by immune gene loss and body remodeling in the pygmy seahorse
inferred← citeshttps://doi.org/10.1099/mgen.0.000675openalex-snapshot
Hospital outbreak of carbapenem-resistant Enterobacterales associated with a bla OXA-48 plasmid carried mostly by Escherichia coli ST399
inferred← citeshttps://doi.org/10.1109/3dic.2013.6702399openalex-snapshot
TSV-based, modular and collision detectable face-to-back shared bus design
inferred← citeshttps://doi.org/10.1109/dsd.2012.135openalex-snapshot
TSV-virtualization for Multi-protocol-Interconnect in 3D-ICs
inferred← citeshttps://doi.org/10.1109/hpcsim.2012.6266923openalex-snapshot
Deadlock-free routing algorithms for 3-dimension Networks-on-Chip with reduced vertical channel density topologies
inferred← citeshttps://doi.org/10.1109/sbcci.2013.6644891openalex-snapshot
Lasio 3D NoC vertical links serialization: Evaluation of latency and buffer occupancy
inferred← citeshttps://doi.org/10.1109/spcom.2018.8724488openalex-snapshot
Floorplan Based Performance Evaluation of 3D Variants of Mesh and BFT Networks-on-Chip
inferred← citeshttps://doi.org/10.1109/tcad.2017.2768415openalex-snapshot
Vertical Arbitration-Free 3-D NoCs
inferred← citeshttps://doi.org/10.1109/tencon.2012.6412341openalex-snapshot
Parameterized path-based, randomized, oblivious, minimal routing in 3D mesh NoC
inferred← citeshttps://doi.org/10.1111/1755-0998.13338openalex-snapshot
Chromosome‐level assembly of southern catfish (silurus meridionalis) provides insights into visual adaptation to nocturnal and benthic lifestyles
inferred← citeshttps://doi.org/10.1186/s12866-021-02253-8openalex-snapshot
Characterization of a bacterial strain Lactobacillus paracasei LP10266 recovered from an endocarditis patient in Shandong, China
inferred← citeshttps://doi.org/10.1371/journal.pcbi.1006994openalex-snapshot
Modern technologies and algorithms for scaffolding assembled genomes
inferred← citeshttps://doi.org/10.3390/antibiotics13080762openalex-snapshot
Rapid Reversal of Carbapenemase-Producing Pseudomonas aeruginosa Epidemiology from blaVIM- to blaNDM-harbouring Isolates in a Greek Tertiary Care Hospital
inferred← citeshttps://doi.org/10.7554/elife.63167openalex-snapshot
High-quality carnivoran genomes from roadkill samples enable comparative species delineation in aardwolf and bat-eared fox
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