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Implementing caches in a 3D technology for high performance processors
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1016/s0167-9260(98)00006-6openalex-snapshot
VLSI design in the 3rd dimension
inferredcites →https://doi.org/10.1109/2.982917openalex-snapshot
SimpleScalar: an infrastructure for computer system modeling
inferredcites →https://doi.org/10.1109/40.782564openalex-snapshot
Design challenges of technology scaling
inferredcites →https://doi.org/10.1109/5.915377openalex-snapshot
Coming challenges in microarchitecture and architecture
inferredcites →https://doi.org/10.1109/92.902261openalex-snapshot
System-level performance evaluation of three-dimensional integrated circuits
inferredcites →https://doi.org/10.1109/aspdac.2004.1337617openalex-snapshot
2.5D system integration: a design driven system implementation schema
inferredcites →https://doi.org/10.1109/aspdac.2005.1466197openalex-snapshot
Floorplanning for 3-D VLSI design
inferredcites →https://doi.org/10.1109/iccad.2003.1257591openalex-snapshot
Efficient thermal placement of standard cells in 3D ICs using a force directed approach
inferredcites →https://doi.org/10.1109/iccd.2004.1347939openalex-snapshot
3D processing technology and its impact on iA32 microprocessors
inferredcites →https://doi.org/10.1109/icicdt.2005.1502578openalex-snapshot
Design aspects of a microprocessor data cache using 3D die interconnect technology
inferredcites →https://doi.org/10.1109/iedm.2002.1175992openalex-snapshot
Electrical integrity of state-of-the-art 0.13 μm SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication
inferredcites →https://doi.org/10.1109/isca.2000.854395openalex-snapshot
Clock rate versus IPC: the end of the road for conventional microarchitectures
inferredcites →https://doi.org/10.1109/iscas.2000.855998openalex-snapshot
An analytical 3-D placement that reserves routing space
inferredcites →https://doi.org/10.1109/ispass.2001.990668openalex-snapshot
MASE: a novel infrastructure for detailed microarchitectural modeling
inferredcites →https://doi.org/10.1109/isqed.2002.996687openalex-snapshot
Fabrication technologies for three-dimensional integrated circuits
inferredcites →https://doi.org/10.1109/isvlsi.2003.1183348openalex-snapshot
Three-dimensional integrated circuits: performance, design methodology, and CAD tools
inferredcites →https://doi.org/10.1109/pact.2003.1238020openalex-snapshot
Picking statistically valid and early simulation points
inferredcites →https://doi.org/10.1109/vlsit.2003.1221088openalex-snapshot
A functional 0.69 μm/sup 2/ embedded 6T-SRAM bit cell for 65 nm CMOS platform
inferredcites →https://doi.org/10.1145/1120725.1120787openalex-snapshot
Thermal-driven multilevel routing for 3-D ICs
inferredcites →https://doi.org/10.1145/1120725.1120899openalex-snapshot
Floorplanning for 3-D VLSI design
inferredcites →https://doi.org/10.1145/764808.764846openalex-snapshot
3D direct vertical interconnect microprocessors test vehicle
inferredcites →https://doi.org/10.1145/981066.981091openalex-snapshot
Technology, performance, and computer-aided design of three-dimensional integrated circuits
inferredcites →https://doi.org/10.5555/1015090.1015203openalex-snapshot
2.5D system integration: a design driven system implementation schema
inferredcites →https://doi.org/10.5555/942806.943854openalex-snapshot
Picking statistically valid and early simulation points
inferredcites →https://doi.org/10.5555/996070.1009873openalex-snapshot
Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Three-Dimensional Microprocessor Design
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Microprocessor Design Using 3D Integration Technology
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Multi-Core Cache Hierarchies
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Power Consumption and Performance Analysis of 3D NoCs
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Thermal-Aware Floorplan Schemes for Reliable 3D Multi-core Processors
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Thermal Modeling and Management of Liquid-Cooled 3D Stacked Architectures
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Adaptive Dynamic Frequency Scaling for Thermal-Aware 3D Multi-core Processors
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Design and Management of 3D Chip Multiprocessors Using Network-In-Memory (NetInMem) [43]
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Another dimension in integrated circuit trust
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3D NOC for many-core processors
inferred← citeshttps://doi.org/10.1016/j.micpro.2016.07.009openalex-snapshot
High-performance processor design based on 3D on-chip cache
inferred← citeshttps://doi.org/10.1049/iet-cdt.2015.0198openalex-snapshot
Collaborative fuzzy‐based partially‐throttling dynamic thermal management scheme for three‐dimensional networks‐on‐chip
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Maximising energy efficiency in 3D multicore systems: a formalised approach
inferred← citeshttps://doi.org/10.1109/3dic.2013.6702346openalex-snapshot
3D cache hierarchy optimization
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3D SRAM Design & Optimization with Open Source Memory Compiler
inferred← citeshttps://doi.org/10.1109/apccas.2010.5774741openalex-snapshot
High-performance 3D-SRAM architecture design
inferred← citeshttps://doi.org/10.1109/aspdac.2011.5722211openalex-snapshot
OPAL: A multi-layer hybrid photonic NoC for 3D ICs
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A new architecture design of three dimensional (3D) Cache
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A novel DRAM architecture as a low leakage alternative for SRAM caches in a 3D interconnect context.
inferred← citeshttps://doi.org/10.1109/ectc.2011.5898694openalex-snapshot
Novel thinning/backside passivation for substrate coupling depression of 3D IC
inferred← citeshttps://doi.org/10.1109/hpca.2007.346197openalex-snapshot
Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors
inferred← citeshttps://doi.org/10.1109/iccd.2009.5413115openalex-snapshot
The impact of liquid cooling on 3D multi-core processors
inferred← citeshttps://doi.org/10.1109/icdipc.2015.7323014openalex-snapshot
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MIRA: A Multi-layered On-Chip Interconnect Router Architecture
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A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies
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The impact of 3-dimensional integration on the design of arithmetic units
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inferred← citeshttps://doi.org/10.1109/isqed.2007.76openalex-snapshot
FinFET Based SRAM Design for Low Standby Power Applications
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A convex optimization framework for leakage aware thermal provisioning in 3D multicore architectures
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Effective thermal control techniques for liquid-cooled 3D multi-core processors
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Implementing Register Files for High-Performance Microprocessors in a Die-Stacked (3D) Technology
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High Performance Non-blocking Switch Design in 3D Die-Stacking Technology
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A novel 3D crossbar-based chip multiprocessor architecture
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3-D Technology Assessment: Path-Finding the Technology/Design Sweet-Spot
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8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology
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A 3-D IC for Mitigating Energy of Memory Accessing and Data Movement in Accelerator- Based Streaming Architectures
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Reliability and Power Optimization in 3D-Stacked Cache Using a Run-Time Reconfiguration Procedure
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Die Stacking (3D) Microarchitecture
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Leveraging 3D Technology for Improved Reliability
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Processor Design in 3D Die-Stacking Technologies
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2018 Maurice Wilkes Award Given to Gabriel Loh
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Reliability and performance-aware 3D SRAM design
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Ultra high density 3D SRAM cell design in Stacked Horizontal Nanowire (SN3D) fabric
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An analysis of designing 2D/3D chip multiprocessor wit different cache architecture
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Practical Near-Data Processing for In-Memory Analytics Frameworks
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DeVAS: Decoupled Virtual Address Spaces
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3D-Integrated SRAM Components for High-Performance Microprocessors
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An Energy-Efficient Last-Level Cache Architecture for Process Variation-Tolerant 3D Microprocessors
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MRAM-Based Cache System Design and Policy Optimization for RISC-V Multi-Core CPUs
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Design of Hierarchical Cache With Hybrid SOT- and STT-MRAM in Multi-Core CPU Environments
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Stack Aware Threshold Voltage Assignment in 3-D Multicore Designs
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Thermal analysis of a 3D die-stacked high-performance microprocessor
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Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
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Hardware assistance for trustworthy systems through 3-D integration
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Efficiently enabling conventional block sizes for very large die-stacked DRAM caches
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Exploration of heuristic scheduling algorithms for 3D multicore processors
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Spatial and temporal thermal characterization of stacked multicore architectures
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Alleviate Chip Pin Constraint for Multicore Processor by On/Off-Chip Power Delivery System Codesign
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Wafer-level 3D integration technology
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Multi-Core Cache Hierarchies
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Design methodologies and digital circuit implementation for 3DIC wireless sensor node (WSN) system
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Fuzzy-Based Thermal Management Scheme for 3D Chip Multicores with Stacked Caches
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A novel DRAM architecture as a low leakage alternative for SRAM caches in a 3D interconnect context
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OPAL: a multi-layer hybrid photonic NoC for 3D ICs
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Quantifying Architectural Impact of Liquid Cooling for 3D Multi-Core Processors
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