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ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/12.795218openalex-snapshot
A chip-multiprocessor architecture with speculative multithreading
inferredcites →https://doi.org/10.1109/hpca.1998.650541openalex-snapshot
The potential for using thread-level data speculation to facilitate automatic parallelization
inferredcites →https://doi.org/10.1109/hpca.2002.995699openalex-snapshot
Improving value communication for thread-level speculation
inferredcites →https://doi.org/10.1109/hpca.2003.1183532openalex-snapshot
Runahead execution: an alternative to very large instruction windows for out-of-order processors
inferredcites →https://doi.org/10.1109/hpca.2004.10008openalex-snapshot
Out-of-Order Commit Processors
inferredcites →https://doi.org/10.1109/hpca.2004.10011openalex-snapshot
Understanding Scheduling Replay Schemes
inferredcites →https://doi.org/10.1109/hpca.2005.9openalex-snapshot
Checkpointed early load retirement
inferredcites →https://doi.org/10.1109/isca.1998.694770openalex-snapshot
Memory dependence prediction using store sets
inferredcites →https://doi.org/10.1109/isca.2000.854380openalex-snapshot
Wattch: a framework for architectural-level power analysis and optimizations
inferredcites →https://doi.org/10.1109/isca.2002.1003588openalex-snapshot
Difficult-path branch prediction using subordinate microthreads
inferredcites →https://doi.org/10.1109/l-ca.2004.3openalex-snapshot
CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction
inferredcites →https://doi.org/10.1109/micro.1997.645815openalex-snapshot
The predictability of data values
inferredcites →https://doi.org/10.1109/micro.2002.1176234openalex-snapshot
Cherry: Checkpointed early resource recycling in out-of-order microprocessors
inferredcites →https://doi.org/10.1109/micro.2003.1253246openalex-snapshot
Checkpoint processing and recovery: towards scalable large instruction window processors
inferredcites →https://doi.org/10.1109/mm.2004.71openalex-snapshot
Continual flow pipelines: achieving resource-efficient latency tolerance
inferredcites →https://doi.org/10.1145/1024393.1024408openalex-snapshot
Scalable selective re-execution for EDGE architectures
inferredcites →https://doi.org/10.1145/1088149.1088173openalex-snapshot
Tasking with out-of-order spawn in TLS chip multiprocessors
inferredcites →https://doi.org/10.1145/237090.237173openalex-snapshot
Value locality and load value prediction
inferredcites →https://doi.org/10.1145/264107.264189openalex-snapshot
Dynamic speculation and synchronization of data dependences
inferredcites →https://doi.org/10.1145/279358.279378openalex-snapshot
Memory dependence prediction using store sets
inferredcites →https://doi.org/10.1145/291069.291020openalex-snapshot
Data speculation support for a chip multiprocessor
inferredcites →https://doi.org/10.1145/545214.545250openalex-snapshot
Difficult-path branch prediction using subordinate microthreads
inferredcites →https://doi.org/10.1145/782814.782859openalex-snapshot
Enhancing memory level parallelism via recovery-free value prediction
inferredcites →https://doi.org/10.1145/996841.996855openalex-snapshot
Cost effective dynamic program slicing
inferredcites →https://doi.org/10.5555/266800.266824openalex-snapshot
The predictability of data values
inferredcites →https://doi.org/10.5555/563998.564036openalex-snapshot
Speculative lock elision: enabling highly concurrent multithreaded execution
inferredcites →https://doi.org/10.5555/956417.956554openalex-snapshot
Checkpoint processing and recovery: towards scalable large instruction window processors
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-319-11194-0_15openalex-snapshot
Dynamically Spawning Speculative Threads to Improve Speculative Path Execution
inferred← citeshttps://doi.org/10.1007/978-3-540-75444-2_45openalex-snapshot
Speculative Parallelization – Eliminating the Overhead of Failure
inferred← citeshttps://doi.org/10.1007/978-3-642-00904-4_13openalex-snapshot
Reexecution and Selective Reuse in Checkpoint Processors
inferred← citeshttps://doi.org/10.1016/j.ins.2018.03.029openalex-snapshot
Performance and energy optimisation in CPUs through fuzzy knowledge representation
inferred← citeshttps://doi.org/10.1049/iet-cdt.2011.0116openalex-snapshot
Multi-objective optimisations for a superscalar architecture with selective value prediction
inferred← citeshttps://doi.org/10.1109/hipc.2011.6152735openalex-snapshot
Increasing the energy efficiency of TLS systems using intermediate checkpointing
inferred← citeshttps://doi.org/10.1109/hpca.2009.4798281openalex-snapshot
iCFP: Tolerating all-level cache misses in in-order processors
inferred← citeshttps://doi.org/10.1109/hpca.2010.5416634openalex-snapshot
BOLT: Energy-efficient Out-of-Order Latency-Tolerant execution
inferred← citeshttps://doi.org/10.1109/hpca.2015.7056031openalex-snapshot
Mascar: Speeding up GPU warps by reducing memory pitstops
inferred← citeshttps://doi.org/10.1109/icis.2012.45openalex-snapshot
Distributed Control Independence for Composable Multi-processors
inferred← citeshttps://doi.org/10.1109/icpp.2007.53openalex-snapshot
Loop-level Speculative Parallelism in Embedded Applications
inferred← citeshttps://doi.org/10.1109/icpp.2008.24openalex-snapshot
Two-Level Reorder Buffers: Accelerating Memory-Bound Applications on SMT Architectures
inferred← citeshttps://doi.org/10.1109/isca.2006.43openalex-snapshot
Tolerating Dependences Between Large Speculative Threads Via Sub-Threads
inferred← citeshttps://doi.org/10.1109/micro.2016.7783737openalex-snapshot
Exploiting semantic commutativity in hardware speculation
inferred← citeshttps://doi.org/10.1109/sbac-pad.2007.23openalex-snapshot
Predicting Loop Termination to Boost Speculative Thread-Level Parallelism in Embedded Applications
inferred← citeshttps://doi.org/10.1109/sbac-pad.2007.37openalex-snapshot
A Component-Oriented Support for Hierarchical MPI Programming on Multi-Cluster Grid Environments
inferred← citeshttps://doi.org/10.1109/tpds.2007.1081openalex-snapshot
CMP Support for Large and Dependent Speculative Threads
inferred← citeshttps://doi.org/10.1109/tpds.2007.70797openalex-snapshot
Mitosis: A Speculative Multithreaded Processor Based on Precomputation Slices
inferred← citeshttps://doi.org/10.1145/1150019.1136504openalex-snapshot
Tolerating Dependences Between Large Speculative Threads Via Sub-Threads
inferred← citeshttps://doi.org/10.1145/1152154.1152192openalex-snapshot
Adaptive reorder buffers for SMT processors
inferred← citeshttps://doi.org/10.1145/1250662.1250717openalex-snapshot
Transparent control independence (TCI)
inferred← citeshttps://doi.org/10.1145/1273440.1250717openalex-snapshot
Transparent control independence (TCI)
inferred← citeshttps://doi.org/10.1145/1274971.1274992openalex-snapshot
An L2-miss-driven early register deallocation for SMT processors
inferred← citeshttps://doi.org/10.1145/1328195.1328201openalex-snapshot
Hiding the misprediction penalty of a resource-efficient high-performance processor
inferred← citeshttps://doi.org/10.1145/1366230.1366274openalex-snapshot
Improving single-thread performance with fine-grain state maintenance
inferred← citeshttps://doi.org/10.1145/1455650.1455652openalex-snapshot
Reducing register pressure in SMT processors through L2-miss-driven early register release
inferred← citeshttps://doi.org/10.1145/2304576.2304580openalex-snapshot
Distributed replay protocol for distributed uniprocessors
inferred← citeshttps://doi.org/10.1145/2541228.2541233openalex-snapshot
The design and implementation of heterogeneous multicore systems for energy-efficient speculative thread execution
inferred← citeshttps://doi.org/10.5821/dissertation-2117-93299openalex-snapshot
Power- and Performance - Aware Architectures
inferred← citeshttps://doi.org/10.5821/dissertation-2117-94982openalex-snapshot
Mitosis based speculative multithreaded architectures
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