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Security Rule Checking in IC Design
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/dft.2013.6653605openalex-snapshot
Analyzing circuit vulnerability to hardware Trojan insertion at the behavioral level
inferredcites →https://doi.org/10.1109/dftvs.2005.58openalex-snapshot
Securing Scan Design Using Lock and Key Technique
inferredcites →https://doi.org/10.1109/hst.2015.7140240openalex-snapshot
TVVF: Estimating the vulnerability of hardware cryptosystems against timing violation attacks
inferredcites →https://doi.org/10.1109/hst.2016.7495575openalex-snapshot
A layout-driven framework to assess vulnerability of ICs to microprobing attacks
inferredcites →https://doi.org/10.1109/iccd.2013.6657085openalex-snapshot
On design vulnerability analysis and trust benchmarks development
inferredcites →https://doi.org/10.1109/sp.2007.28openalex-snapshot
Moats and Drawbridges: An Isolation Primitive for Reconfigurable Hardware Based Systems
inferredcites →https://doi.org/10.1109/test.2015.7342387openalex-snapshot
Hardware Trojans hidden in RTL don't cares — Automated insertion and prevention methodologies
inferredcites →https://doi.org/10.1145/2366231.2337172openalex-snapshot
Side-channel vulnerability factor
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-030-64448-2_7openalex-snapshot
CAD for Side-Channel Leakage Assessment
inferred← citeshttps://doi.org/10.1007/978-3-030-69131-8_1openalex-snapshot
Trustworthy System-on-Chip Design Using Secure on-Chip Communication Architectures
inferred← citeshttps://doi.org/10.1007/978-3-031-37989-5_5openalex-snapshot
Fundamentals of Logic Locking
inferred← citeshttps://doi.org/10.1007/978-3-319-49025-0_15openalex-snapshot
The Future of Trustworthy SoC Design
inferred← citeshttps://doi.org/10.1007/s11227-021-03927-wopenalex-snapshot
Power side-channel leakage assessment and locating the exact sources of leakage at the early stages of ASIC design process
inferred← citeshttps://doi.org/10.1007/s41635-017-0002-5openalex-snapshot
Security Assurance Guidance for Third-Party IP
inferred← citeshttps://doi.org/10.1016/b978-0-12-812477-2.00011-3openalex-snapshot
Electronics Supply Chain
inferred← citeshttps://doi.org/10.1016/b978-0-12-812477-2.00018-6openalex-snapshot
Security and Trust Assessment, and Design for Security
inferred← citeshttps://doi.org/10.1016/j.sysarc.2022.102543openalex-snapshot
Is your FPGA bitstream Hardware Trojan-free? Machine learning can provide an answer
inferred← citeshttps://doi.org/10.1109/access.2024.3400685openalex-snapshot
Trustworthy Integrated Circuits: From Safety to Security and Beyond
inferred← citeshttps://doi.org/10.1109/asp-dac58780.2024.10473835openalex-snapshot
Security Coverage Metrics for Information Flow at the System Level
inferred← citeshttps://doi.org/10.1109/dtis53253.2021.9505109openalex-snapshot
Toward an Implementation Modeling Methodology for Designing SCA resilient Cryptographic Circuits
inferred← citeshttps://doi.org/10.1109/emergin67762.2025.11450727openalex-snapshot
Validation of Design Rule Checks using SKILL Automation
inferred← citeshttps://doi.org/10.1109/hst.2019.8740840openalex-snapshot
QIF-Verilog: Quantitative Information-Flow based Hardware Description Languages for Pre-Silicon Security Assessment
inferred← citeshttps://doi.org/10.1109/iccad57390.2023.10323687openalex-snapshot
SystemC Model of Power Side-Channel Attacks Against AI Accelerators: Superstition or not?
inferred← citeshttps://doi.org/10.1109/tc.2019.2900235openalex-snapshot
The Security of ARM TrustZone in a FPGA-Based SoC
inferred← citeshttps://doi.org/10.1109/tcad.2018.2834396openalex-snapshot
Security-Aware FSM Design Flow for Identifying and Mitigating Vulnerabilities to Fault Attacks
inferred← citeshttps://doi.org/10.1109/tcad.2021.3063998openalex-snapshot
SoFI: Security Property-Driven Vulnerability Assessments of ICs Against Fault-Injection Attacks
inferred← citeshttps://doi.org/10.1109/test.2017.8242062openalex-snapshot
Hardware trojan detection through information flow security verification
inferred← citeshttps://doi.org/10.1109/vts.2019.8758600openalex-snapshot
RTL-PSC: Automated Power Side-Channel Leakage Assessment at Register-Transfer Level
inferred← citeshttps://doi.org/10.1145/3563391openalex-snapshot
A Survey and Perspective on Artificial Intelligence for Security-Aware Electronic Design Automation
inferred← citeshttps://doi.org/10.1145/3576199openalex-snapshot
Challenges and Opportunities of Security-Aware EDA
inferred← citeshttps://doi.org/10.1145/3706594.3728869openalex-snapshot
Leveraging gem5 for Hardware Trojan Research: Simulation for Machine-Learning-Based Detection
inferred← citeshttps://doi.org/10.23919/date54114.2022.9774694openalex-snapshot
Inter-IP Malicious Modification Detection through Static Information Flow Tracking
inferred← citeshttps://doi.org/10.5220/0012324200003648openalex-snapshot
Machine Learning-Based Classification of Hardware Trojans in FPGAs Implementing RISC-V Cores
inferred← citeshttps://doi.org/10.70675/7c887878z5a2fz44c9z979az1d7fcc339b6aopenalex-snapshot
Design for security in mixed analog-digital integrated circuits
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