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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/11894063_14openalex-snapshot
A Proposition for Correlation Power Analysis Enhancement
inferredcites →https://doi.org/10.1007/978-3-319-42438-5_15openalex-snapshot
Power Analysis and Optimization
inferredcites →https://doi.org/10.1007/978-3-319-49025-0openalex-snapshot
Hardware IP Security and Trust
inferredcites →https://doi.org/10.1007/978-3-319-78375-8_11openalex-snapshot
Formal Verification of Masked Hardware Implementations in the Presence of Glitches
inferredcites →https://doi.org/10.1007/978-3-540-28632-5_2openalex-snapshot
Correlation Power Analysis with a Leakage Model
inferredcites →https://doi.org/10.1007/978-3-540-45238-6_11openalex-snapshot
Securing Encryption Algorithms against DPA at the Logic Level: Next Generation Smart Card Technology
inferredcites →https://doi.org/10.1007/978-3-540-85053-3_27openalex-snapshot
Mutual Information Analysis
inferredcites →https://doi.org/10.1007/978-3-642-04138-9_30openalex-snapshot
Mutual Information Analysis: How, When and Why?
inferredcites →https://doi.org/10.1007/978-3-642-40349-1_17openalex-snapshot
Sleuth: Automated Verification of Software Power Analysis Countermeasures
inferredcites →https://doi.org/10.1007/978-3-662-46800-5_18openalex-snapshot
Verified Proofs of Higher-Order Masking
inferredcites →https://doi.org/10.1007/978-3-662-49890-3_10openalex-snapshot
From Improved Leakage Detection to the Detection of Points of Interests in Leakage Traces
inferredcites →https://doi.org/10.1007/b117406openalex-snapshot
Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits
inferredcites →https://doi.org/10.1016/j.jksuci.2014.03.005openalex-snapshot
Power estimation for intellectual property-based digital systems at the architectural level
inferredcites →https://doi.org/10.1109/aspdac.2017.7858392openalex-snapshot
Security vulnerability analysis of design-for-test exploits for asset protection in SoCs
inferredcites →https://doi.org/10.1109/cse.2009.119openalex-snapshot
A Smart Card Power Analysis Simulator
inferredcites →https://doi.org/10.1109/dft.2015.7315143openalex-snapshot
Security analysis of logic encryption against the most effective side-channel attack: DPA
inferredcites →https://doi.org/10.1109/hst.2011.5955000openalex-snapshot
Algorithmic collision analysis for evaluating cryptographic systems and side-channel attacks
inferredcites →https://doi.org/10.1109/hst.2018.8383894openalex-snapshot
Horizontal side-channel vulnerabilities of post-quantum key exchange protocols
inferredcites →https://doi.org/10.1109/iscas.2006.1693233openalex-snapshot
Side Channel Analysis Resistant Design Flow
inferredcites →https://doi.org/10.1109/mc.2016.226openalex-snapshot
Security Rule Checking in IC Design
inferredcites →https://doi.org/10.1109/tc.2002.1004593openalex-snapshot
Examining smart-card security under the threat of power analysis attacks
inferredcites →https://doi.org/10.1109/tc.2013.219openalex-snapshot
Automatic Application of Power Analysis Countermeasures
inferredcites →https://doi.org/10.1109/test.2017.8242062openalex-snapshot
Hardware trojan detection through information flow security verification
inferredcites →https://doi.org/10.1145/2024724.2024778openalex-snapshot
A first step towards automatic application of power analysis countermeasures
inferredcites →https://doi.org/10.1145/2676548openalex-snapshot
Gate-Level Information Flow Tracking for Security Lattices
inferredcites →https://doi.org/10.3390/jlpea7010004openalex-snapshot
A Novel Design Flow for a Security-Driven Synthesis of Side-Channel Hardened Cryptographic Modules
inferredcites →https://doi.org/10.46586/tches.v2018.i1.209-237openalex-snapshot
Leakage Detection with the x2-Test
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-030-64448-2_7openalex-snapshot
CAD for Side-Channel Leakage Assessment
inferred← citeshttps://doi.org/10.1007/978-3-030-89915-8_6openalex-snapshot
Protecting Secure ICs Against Side-Channel Attacks by Identifying and Quantifying Potential EM and Leakage Hotspots at Simulation Stage
inferred← citeshttps://doi.org/10.1007/978-3-031-26896-0_18openalex-snapshot
The Future of CAD for Hardware Security
inferred← citeshttps://doi.org/10.1007/978-3-031-26896-0_2openalex-snapshot
CAD for Security Asset Identification
inferred← citeshttps://doi.org/10.1007/978-3-031-26896-0_6openalex-snapshot
CAD for Power Side-Channel Detection
inferred← citeshttps://doi.org/10.1007/978-3-031-31034-8_8openalex-snapshot
Power Analysis Attacks on AES
inferred← citeshttps://doi.org/10.1007/978-3-031-58687-3_1openalex-snapshot
Quantifiable Assurance in Hardware
inferred← citeshttps://doi.org/10.1007/978-3-031-58687-3_4openalex-snapshot
SoC Security Verification Using Fuzz, Penetration, and AI Testing
inferred← citeshttps://doi.org/10.1007/978-3-031-58687-3_8openalex-snapshot
Digital Twin for Secure Semiconductor Lifecycle Management
inferred← citeshttps://doi.org/10.1007/978-3-032-23844-3_10openalex-snapshot
A Comprehensive Survey on System-on-Chip Security Risks and Mitigation Techniques
inferred← citeshttps://doi.org/10.1007/978-981-15-6401-7_42-1openalex-snapshot
Information Flow Verification
inferred← citeshttps://doi.org/10.1007/978-981-97-9314-3_42openalex-snapshot
Information Flow Verification
inferred← citeshttps://doi.org/10.1007/s13389-025-00386-4openalex-snapshot
Netlist whisperer: extensive analysis of circuit leakage using LLMs
inferred← citeshttps://doi.org/10.1016/b978-0-44-318754-4.00028-4openalex-snapshot
Quantifiable assurance: from IPs to SoCs
inferred← citeshttps://doi.org/10.1038/s44287-026-00296-5openalex-snapshot
Cybersecurity vulnerabilities in IoT devices
inferred← citeshttps://doi.org/10.1109/asp-dac52403.2022.9712551openalex-snapshot
FORTIFY: Analytical Pre-Silicon Side-Channel Characterization of Digital Designs
inferred← citeshttps://doi.org/10.1109/dac18074.2021.9586210openalex-snapshot
PSC-TG: RTL Power Side-Channel Leakage Assessment with Test Pattern Generation
inferred← citeshttps://doi.org/10.1109/dsd60849.2023.00022openalex-snapshot
A Pre-Silicon Power Leakage Assessment Based on Generative Adversarial Networks
inferred← citeshttps://doi.org/10.1109/eurospw59978.2023.00036openalex-snapshot
Emulating Side Channel Attacks on gem5: lessons learned
inferred← citeshttps://doi.org/10.1109/iscas56072.2025.11043283openalex-snapshot
Physical Design-Aware Power Side-Channel Leakage Assessment Framework using Deep Learning
inferred← citeshttps://doi.org/10.1109/iseda65950.2025.11100836openalex-snapshot
Pre-Silicon Power Side-Channel Leakage Assessment Through Quantitative Information Flow Analysis
inferred← citeshttps://doi.org/10.1109/isqed51717.2021.9424365openalex-snapshot
Secure High-Level Synthesis: Challenges and Solutions
inferred← citeshttps://doi.org/10.1109/jiot.2026.3659185openalex-snapshot
HScanner: A Knowledge-Driven Framework for Early-Stage Detection of Hardware Vulnerabilities in IIoT Devices
inferred← citeshttps://doi.org/10.1109/jiot.2026.3697699openalex-snapshot
Compact ASIC Design of a Secure Hexadecimal Digital Lock for Consumer Electronics
inferred← citeshttps://doi.org/10.1109/naecon61878.2024.10670646openalex-snapshot
Power Side-Channel Verification in Hardware Designs
inferred← citeshttps://doi.org/10.1109/ojcas.2025.3602353openalex-snapshot
A Proxy ADC Framework for Side-Channel Secure ADC Analysis
inferred← citeshttps://doi.org/10.1109/tc.2023.3333164openalex-snapshot
VALIANT: An EDA Flow for Side-Channel Leakage Evaluation and Tailored Protection
inferred← citeshttps://doi.org/10.1109/tcad.2024.3387875openalex-snapshot
Automatic Asset Identification for Assertion-Based SoC Security Verification
inferred← citeshttps://doi.org/10.1109/tetc.2023.3268303openalex-snapshot
Gate-Level Side-Channel Leakage Ranking With Architecture Correlation Analysis
inferred← citeshttps://doi.org/10.1109/tvlsi.2022.3175067openalex-snapshot
Power Side-Channel Leakage Assessment Framework at Register-Transfer Level
inferred← citeshttps://doi.org/10.1109/vts50974.2021.9441039openalex-snapshot
SAIF: Automated Asset Identification for Security Verification at the Register Transfer Level
inferred← citeshttps://doi.org/10.1145/3568957openalex-snapshot
Silicon-correlated Simulation Methodology of EM Side-channel Leakage Analysis
inferred← citeshttps://doi.org/10.1145/3721294openalex-snapshot
CTScan: A CGRA-based Platform for the Emulation of Power Side-Channel Attacks on Edge CPUs
inferred← citeshttps://doi.org/10.1145/3768154openalex-snapshot
Boosting Cryptographic ICs’ Side-Channel Resistance: A Formal Framework for Automatic Identification and Protection of Leaky Paths
inferred← citeshttps://doi.org/10.1145/3768725.3768730openalex-snapshot
Enabling Gem5 for Side-Channel Power Attack Simulation of Cryptographic Algorithms
inferred← citeshttps://doi.org/10.1145/3806057openalex-snapshot
GED-Net: A Multi-modal Reconstruction Network for CAD Parametric Models based on Grouped Entity Decoding
inferred← citeshttps://doi.org/10.3390/chips3040016openalex-snapshot
PreSCAN: A Comprehensive Review of Pre-Silicon Physical Side-Channel Vulnerability Assessment Methodologies
inferred← citeshttps://doi.org/10.3390/jlpea15040066openalex-snapshot
Research on the Security of SRAM-Based FPGAs in the Era of Artificial Intelligence
inferred← citeshttps://doi.org/10.48550/arxiv.2104.08593openalex-snapshot
SoK: Design Tools for Side-Channel-Aware Implementations
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