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A Survey and Perspective on Artificial Intelligence for Security-Aware Electronic Design Automation
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Satisfiability Don't Care condition based circuit fingerprinting techniques
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1989 Proceedings of the IEEE Custom Integrated Circuits Conference
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Parametric counterfeit IC detection via Support Vector Machines
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Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning
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Pyramid: Machine Learning Framework to Estimate the Optimal Timing and Resource Usage of a High-Level Synthesis Design
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Machine learning resistant strong PUF: Possible or a pipe dream?
inferredcites →https://doi.org/10.1109/hst.2017.7951805openalex-snapshot
AppSAT: Approximately deobfuscating integrated circuits
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LSOracle: a Logic Synthesis Framework Driven by Artificial Intelligence: Invited Paper
inferredcites →https://doi.org/10.1109/icecs.2003.1301804openalex-snapshot
Proceedings of the 2003 10th IEEE International Conference on Electronics, Circuits and Systems - ICECS 2003
inferredcites →https://doi.org/10.1109/icecs.2014.7050096openalex-snapshot
RF-LNA circuit synthesis by genetic algorithm-specified artificial neural network
inferredcites →https://doi.org/10.1109/icvd.2005.47openalex-snapshot
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inferredcites →https://doi.org/10.1109/iscas.2015.7168698openalex-snapshot
RF-LNA circuit synthesis using an array of artificial neural networks with constrained inputs
inferredcites →https://doi.org/10.1109/isesd.2017.8253353openalex-snapshot
Prediction of element values of OPAmp for required specifications utilizing deep learning
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Approximate Logic Synthesis: A Reinforcement Learning-Based Technology Mapping Approach
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Built-In Self Optimization for Variation Resilience of Analog Filters
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Introducing Recurrence in Strong PUFs for Enhanced Machine Learning Attack Resistance
inferredcites →https://doi.org/10.1109/jproc.2005.862424openalex-snapshot
The Sorcerer's Apprentice Guide to Fault Attacks
inferredcites →https://doi.org/10.1109/jproc.2014.2320516openalex-snapshot
Physical Unclonable Functions and Applications: A Tutorial
inferredcites →https://doi.org/10.1109/mc.2016.226openalex-snapshot
Security Rule Checking in IC Design
inferredcites →https://doi.org/10.1109/mdat.2017.2729398openalex-snapshot
Probing Attacks on Integrated Circuits: Challenges and Research Opportunities
inferredcites →https://doi.org/10.1109/mdat.2020.3024153openalex-snapshot
MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII
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Split-Chip Design to Prevent IP Reverse Engineering
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A Survey of Hardware Trojan Taxonomy and Detection
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Geometric Deep Learning: Going beyond Euclidean data
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Federated Learning: Challenges, Methods, and Future Directions
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Bogus: electronic manufacturing and consumers confront a rising tide of counterfeit electronics
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Fast and Scalable I/O Pin Assignment with Divide-and-Conquer and Hungarian Matching
inferredcites →https://doi.org/10.1109/socpar.2010.5686736openalex-snapshot
Design optimization of analog integrated circuits by using artificial neural networks
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Sequential Circuit Design for Embedded Cryptographic Applications Resilient to Adversarial Faults
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Statistical Analysis of Second Order Differential Power Analysis
inferredcites →https://doi.org/10.1109/tc.2013.193openalex-snapshot
Fault Analysis-Based Logic Encryption
inferredcites →https://doi.org/10.1109/tcad.2002.806600openalex-snapshot
Extraction and use of neural network models in automated synthesis of operational amplifiers
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HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection
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High-Level Synthesis for FPGAs: From Prototyping to Deployment
inferredcites →https://doi.org/10.1109/tcad.2014.2360458openalex-snapshot
Fast Monte Carlo-Based Estimation of Analog Parametric Test Metrics
inferredcites →https://doi.org/10.1109/tcad.2015.2428707openalex-snapshot
Belling the CAD: Toward Security-Centric Electronic System Design
inferredcites →https://doi.org/10.1109/tcad.2015.2449240openalex-snapshot
Harvesting Design Knowledge From the Internet: High-Dimensional Performance Tradeoff Modeling for Large-Scale Analog Circuits
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Bayesian Model Fusion: Large-Scale Performance Modeling of Analog and Mixed-Signal Circuits by Reusing Early-Stage Data
inferredcites →https://doi.org/10.1109/tcad.2018.2834396openalex-snapshot
Security-Aware FSM Design Flow for Identifying and Mitigating Vulnerabilities to Fault Attacks
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Obfuscated Built-In Self-Authentication With Secure and Efficient Wire-Lifting
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Real-Time Detection of Power Analysis Attacks by Machine Learning of Power Supply Variations On-Chip
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Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock Distribution
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An Artificial Neural Network Assisted Optimization System for Analog Design Space Exploration
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Security-Driven Placement and Routing Tools for Electromagnetic Side-Channel Protection
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Current Mirror Array: A Novel Circuit Topology for Combining Physical Unclonable Function and Machine Learning
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Ask Less, Get More: Side-Channel Signal Hiding, Revisited
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A Survey of Optimization Methods From a Machine Learning Perspective
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Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction
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I Choose You: Automated Hyperparameter Tuning for Deep Learning-Based Side-Channel Analysis
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Security Implications of Intentional Capacitive Crosstalk
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SARO: Scalable Attack-Resistant Logic Locking
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Capturing High-Discriminative Fault Features for Electronics-Rich Analog System via Deep Learning
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A Novel Technique for Improving Hardware Trojan Detection and Reducing Trojan Activation Time
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Design of Accurate Low-Cost On-Chip Structures for Protecting Integrated Circuits Against Recycling
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The Cat and Mouse in Split Manufacturing
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Probing Assessment Framework and Evaluation of Antiprobing Solutions
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Hardware Trojan Detection Using Reconfigurable Assertion Checkers
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RTL Hardware IP Protection Using Key-Based Control and Data Flow Obfuscation
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Automation of Analog IC Layout
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Formal Semantics for Kolmogorov-Arnold Network Representations of Operational Games
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Incoming claims: where this work appears in other papers’ reference lists and arguments.
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