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Mining assumptions for synthesis

https://doi.org/10.1109/memcod.2011.5970509

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

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Reasoning about Infinite Computations

inferredcites →https://doi.org/10.1007/10722167_34openalex-snapshot

Temporal-logic Queries

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Synthesis of Reactive(1) Designs

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Efficient Debugging in a Formal Verification Environment

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Anzu: A Tool for Property Synthesis

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Diagnostic Information for Realizability

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Environment Assumptions for Synthesis

inferredcites →https://doi.org/10.1007/978-3-642-14295-6_37openalex-snapshot

RATSY – A New Requirements Analysis Tool with Synthesis

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Gist: A Solver for Probabilistic Games

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Variants of LTL Query Checking

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Debugging Unrealizable Specifications with Model-Based Diagnosis

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Recognizing safety and liveness

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Efficient debugging in a formal verification environment

inferredcites →https://doi.org/10.1016/j.entcs.2007.09.004openalex-snapshot

Specify, Compile, Run: Hardware from PSL

inferredcites →https://doi.org/10.1016/j.jcss.2011.08.007openalex-snapshot

Synthesis of Reactive(1) designs

inferredcites →https://doi.org/10.1016/j.scico.2007.01.015openalex-snapshot

The Daikon system for dynamic detection of likely invariants

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Extracting Environmental Constraints to Make Reactive System Specifications Realizable

inferredcites →https://doi.org/10.1109/csd.2003.1207698openalex-snapshot

Synthesis of open reactive systems from scenario-based specifications

inferredcites →https://doi.org/10.1109/date.2007.364456openalex-snapshot

Automatic Hardware Synthesis from Specifications: A Case Study

inferredcites →https://doi.org/10.1109/fmcad.2006.22openalex-snapshot

Optimizations for LTL Synthesis

inferredcites →https://doi.org/10.1109/fmcad.2009.5351127openalex-snapshot

Debugging formal specifications using simple counterstrategies

inferredcites →https://doi.org/10.1109/lics.2006.28openalex-snapshot

From Nondeterministic Buchi and Streett Automata to Deterministic Parity Automata

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Synthesis of interface specifications for Java classes

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Scalable specification mining for verification and diagnosis

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The synthesis of loop predicates

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Model exploration with temporal logic query checking

inferredcites →https://doi.org/10.1145/75277.75293openalex-snapshot

On the synthesis of a reactive module

inferredcites →https://doi.org/10.5555/1266366.1266622openalex-snapshot

Interactive presentation: Automatic hardware synthesis from specifications: a case study

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Formal Methods for Design and Verification of Embedded Control Systems: Application to an Autonomous Vehicle

What points at this work

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Environmental Assumptions in System Design: A Phenomenon-Based and Operational Perspective

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Automated Robot Recovery from Assumption Violations of High-Level Specifications

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Combining Induction, Deduction, and Structure for Verification and Synthesis

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Layering Assume-Guarantee Contracts for Hierarchical System Design

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Physically Feasible Repair of Reactive, Linear Temporal Logic-Based, High-Level Tasks

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Minimal Assumptions Refinement for GR(1) Specifications

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