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Counter-strategy guided refinement of GR(1) temporal logic specifications
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Outgoing claims: the papers this work cites, builds on, or argues with.
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Environment Assumptions for Synthesis
inferredcites →https://doi.org/10.1007/978-3-642-14295-6_37openalex-snapshot
RATSY – A New Requirements Analysis Tool with Synthesis
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Synthesis of Reactive(1) designs
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Distributed power allocation for vehicle management systems
inferredcites →https://doi.org/10.1109/fmcad.2009.5351127openalex-snapshot
Debugging formal specifications using simple counterstrategies
inferredcites →https://doi.org/10.1109/fmcad.2013.6679387openalex-snapshot
Counter-strategy guided refinement of GR(1) temporal logic specifications
inferredcites →https://doi.org/10.1109/memcod.2011.5970509openalex-snapshot
Mining assumptions for synthesis
inferredcites →https://doi.org/10.1109/tac.2012.2195811openalex-snapshot
Receding Horizon Temporal Logic Planning
inferredcites →https://doi.org/10.1145/75277.75293openalex-snapshot
On the synthesis of a reactive module
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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