On the public citation graph
MicroLib: A Case for the Quantitative Comparison of Micro-Architecture Mechanisms
0 signed · 108 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/hpca.2003.1183549openalex-snapshot
TCP: tag correlating prefetchers
inferredcites →https://doi.org/10.1109/hpca.2004.10030openalex-snapshot
Data Cache Prefetching Using a Global History Buffer
inferredcites →https://doi.org/10.1109/icpp.2003.1240590openalex-snapshot
Enabling partial cache line prefetching through data compression
inferredcites →https://doi.org/10.1109/isca.1990.134547openalex-snapshot
Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
inferredcites →https://doi.org/10.1109/isca.1999.765953openalex-snapshot
A performance comparison of contemporary DRAM architectures
inferredcites →https://doi.org/10.1109/micro.1992.697004openalex-snapshot
Stride Directed Prefetching In Scalar Processors
inferredcites →https://doi.org/10.1109/micro.2000.898056openalex-snapshot
A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality
inferredcites →https://doi.org/10.1109/micro.2002.1176250openalex-snapshot
Energy efficient Frequent Value data Cache design
inferredcites →https://doi.org/10.1109/micro.2002.1176256openalex-snapshot
Microarchitectural exploration with Liberty
inferredcites →https://doi.org/10.1145/144965.145006openalex-snapshot
Stride directed prefetching in scalar processors
inferredcites →https://doi.org/10.1145/264107.264207openalex-snapshot
Prefetching using Markov predictors
inferredcites →https://doi.org/10.1145/268806.268810openalex-snapshot
The SimpleScalar tool set, version 2.0
inferredcites →https://doi.org/10.1145/285930.285979openalex-snapshot
Lockup-free instruction fetch/prefetch cache organization
inferredcites →https://doi.org/10.1145/285930.285998openalex-snapshot
Improving direct-mapped cache performance by the addition of a small fully-associative cache prefetch buffers
inferredcites →https://doi.org/10.1145/300979.300998openalex-snapshot
A performance comparison of contemporary DRAM architectures
inferredcites →https://doi.org/10.1145/356989.357003openalex-snapshot
Frequent value locality and value-centric data cache design
inferredcites →https://doi.org/10.1145/360128.360132openalex-snapshot
Eager writeback - a technique for improving bandwidth utilization
inferredcites →https://doi.org/10.1145/360128.360134openalex-snapshot
A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality
inferredcites →https://doi.org/10.1145/378993.379235openalex-snapshot
Frequent value locality and value-centric data cache design
inferredcites →https://doi.org/10.1145/379240.379259openalex-snapshot
Dead-block prediction & dead-block correlating prefetchers
inferredcites →https://doi.org/10.1145/383082.383086openalex-snapshot
L1 data cache decomposition for energy efficiency
inferredcites →https://doi.org/10.1145/545214.545239openalex-snapshot
Timekeeping in the memory system
inferredcites →https://doi.org/10.1145/605397.605403openalex-snapshot
Automatically characterizing large scale program behavior
inferredcites →https://doi.org/10.1145/605397.605427openalex-snapshot
A stateless, content-directed data prefetching mechanism
inferredcites →https://doi.org/10.5555/774861.774891openalex-snapshot
Microarchitectural exploration with Liberty
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-1-4419-6175-4_6openalex-snapshot
Structural Simulation for Architecture Exploration
inferred← citeshttps://doi.org/10.1007/978-3-031-01727-8openalex-snapshot
Computer Architecture Performance Evaluation Methods
inferred← citeshttps://doi.org/10.1007/978-3-540-69338-3_12openalex-snapshot
Sunflower : Full-System, Embedded Microarchitecture Evaluation
inferred← citeshttps://doi.org/10.1007/978-3-540-85451-7_36openalex-snapshot
Low-Cost Adaptive Data Prefetching
inferred← citeshttps://doi.org/10.1007/978-3-642-11515-8_19openalex-snapshot
Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching
inferred← citeshttps://doi.org/10.1007/978-3-642-23400-2_31openalex-snapshot
Using Runtime Activity to Dynamically Filter Out Inefficient Data Prefetches
inferred← citeshttps://doi.org/10.1007/978-94-007-4516-2_11openalex-snapshot
Storage-Efficient Data Prefetching for High Performance Computing
inferred← citeshttps://doi.org/10.1007/s10617-010-9050-6openalex-snapshot
Evaluation of the implementation cost of cache coherence protocols using omniscient actions
inferred← citeshttps://doi.org/10.1007/s11227-014-1088-yopenalex-snapshot
Adaptive prefetching using global history buffer in multicore processors
inferred← citeshttps://doi.org/10.1016/j.micpro.2013.09.004openalex-snapshot
Practical models for energy-efficient prefetching in mobile embedded systems
inferred← citeshttps://doi.org/10.1016/j.micpro.2014.03.010openalex-snapshot
Design of write merging and read prefetching buffer in DRAM controller for embedded processor
inferred← citeshttps://doi.org/10.1016/j.parco.2017.07.007openalex-snapshot
Low-level implementation of the SISC protocol for thread-level speculation on a multi-core architecture
inferred← citeshttps://doi.org/10.1016/j.phpro.2012.03.239openalex-snapshot
Cache Performance Research for Embedded Processors
inferred← citeshttps://doi.org/10.1016/j.simpat.2014.03.005openalex-snapshot
Network aware performance evaluation of prefetching techniques in CMPs
inferred← citeshttps://doi.org/10.1016/s0065-2458(08)00004-1openalex-snapshot
Sampled Processor Simulation: A Survey
inferred← citeshttps://doi.org/10.1093/comjnl/bxv112openalex-snapshot
Why Does Data Prefetching Not Work for Modern Workloads?
inferred← citeshttps://doi.org/10.1109/access.2019.2917698openalex-snapshot
A Survey of Computer Architecture Simulation Techniques and Tools
inferred← citeshttps://doi.org/10.1109/aspdac.2013.6509617openalex-snapshot
An adaptive filtering mechanism for energy efficient data prefetching
inferred← citeshttps://doi.org/10.1109/date.2005.250openalex-snapshot
Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints
inferred← citeshttps://doi.org/10.1109/date.2012.6176515openalex-snapshot
S/DC: A storage and energy efficient data prefetcher
inferred← citeshttps://doi.org/10.1109/hpca.2009.4798232openalex-snapshot
Techniques for bandwidth-efficient prefetching of linked data structures in hybrid prefetching systems
inferred← citeshttps://doi.org/10.1109/hpca.2010.5416628openalex-snapshot
An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth
inferred← citeshttps://doi.org/10.1109/hpca.2016.7446087openalex-snapshot
Best-offset hardware prefetching
inferred← citeshttps://doi.org/10.1109/hpca.2018.00021openalex-snapshot
Domino Temporal Data Prefetcher
inferred← citeshttps://doi.org/10.1109/icasic.2005.1611459openalex-snapshot
A Technique to Exploit Memory Locality for Fast Instruction Set Simulation
inferred← citeshttps://doi.org/10.1109/ipdps.2005.434openalex-snapshot
TiNy Threads: A Thread Virtual Machine for the Cyclops64 Cellular Architecture
inferred← citeshttps://doi.org/10.1109/isca.2005.50openalex-snapshot
Temporal Streaming of Shared Memory
inferred← citeshttps://doi.org/10.1109/isca.2016.46openalex-snapshot
Accelerating Dependent Cache Misses with an Enhanced Memory Controller
inferred← citeshttps://doi.org/10.1109/ispass.2007.363741openalex-snapshot
Last-Touch Correlated Data Streaming
inferred← citeshttps://doi.org/10.1109/ispass.2009.4919638openalex-snapshot
Zesto: A cycle-level simulator for highly detailed microarchitecture exploration
inferred← citeshttps://doi.org/10.1109/ispass.2010.5452021openalex-snapshot
Runahead execution vs. conventional data prefetching in the IBM POWER6 microprocessor
inferred← citeshttps://doi.org/10.1109/ispass.2010.5452068openalex-snapshot
ArchExplorer.org: A methodology for facilitating a fair Comparison of research ideas
inferred← citeshttps://doi.org/10.1109/l-ca.2007.12openalex-snapshot
UNISIM: An Open Simulation Environment and Library for Complex Architecture Design and Collaborative Development
inferred← citeshttps://doi.org/10.1109/l-ca.2011.2openalex-snapshot
Prefetching in Embedded Mobile Systems Can Be Energy-Efficient
inferred← citeshttps://doi.org/10.1109/mascots.2010.43openalex-snapshot
Barra: A Parallel Functional Simulator for GPGPU
inferred← citeshttps://doi.org/10.1109/micro.2007.23openalex-snapshot
Effective Optimistic-Checker Tandem Core Design through Architectural Pruning
inferred← citeshttps://doi.org/10.1109/micro.2007.39openalex-snapshot
Low-Cost Epoch-Based Correlation Prefetching for Commercial Applications
inferred← citeshttps://doi.org/10.1109/mm.2005.6openalex-snapshot
Data Cache Prefetching Using a Global History Buffer
inferred← citeshttps://doi.org/10.1109/mm.2006.104openalex-snapshot
A Sampling Method Focusing on Practicality
inferred← citeshttps://doi.org/10.1109/mm.2010.76openalex-snapshot
ArchExplorer for Automatic Design Space Exploration
inferred← citeshttps://doi.org/10.1109/pact.2004.1342548openalex-snapshot
AC/DC: an adaptive data cache prefetcher
inferred← citeshttps://doi.org/10.1109/pact.2005.37openalex-snapshot
Store-ordered streaming of shared memory
inferred← citeshttps://doi.org/10.1109/tc.2006.44openalex-snapshot
Simulation of computer architectures: simulators, benchmarks, methodologies, and recommendations
inferred← citeshttps://doi.org/10.1109/tc.2007.17openalex-snapshot
Reducing Cache Pollution via Dynamic Data Prefetch Filtering
inferred← citeshttps://doi.org/10.1109/tc.2007.250620openalex-snapshot
Reducing Cache Pollution via Dynamic Data Prefetch Filtering
inferred← citeshttps://doi.org/10.1109/tc.2012.88openalex-snapshot
Acceleration of XML Parsing through Prefetching
inferred← citeshttps://doi.org/10.1109/tcad.2006.882597openalex-snapshot
Generic Processor Modeling for Automatically Generating Very Fast Cycle-Accurate Simulators
inferred← citeshttps://doi.org/10.1109/tvlsi.2009.2030199openalex-snapshot
Quasi-Static Voltage Scaling for Energy Minimization With Time Constraints
inferred← citeshttps://doi.org/10.1145/1080695.1069989openalex-snapshot
Temporal Streaming of Shared Memory
inferred← citeshttps://doi.org/10.1145/1128022.1128059openalex-snapshot
Kilo-instruction processors, runahead and prefetching
inferred← citeshttps://doi.org/10.1145/1166133.1166138openalex-snapshot
Data prefetching in a cache hierarchy with high bandwidth and capacity
inferred← citeshttps://doi.org/10.1145/1210268.1210271openalex-snapshot
Power-efficient prefetching for embedded processors
inferred← citeshttps://doi.org/10.1145/1242531.1242537openalex-snapshot
Analysis of hardware prefetching across virtual page boundaries
inferred← citeshttps://doi.org/10.1145/1327312.1327319openalex-snapshot
Data prefetching in a cache hierarchy with high bandwidth and capacity
inferred← citeshttps://doi.org/10.1145/1362622.1362651openalex-snapshot
Data access history cache and associated data prefetching mechanisms
inferred← citeshttps://doi.org/10.1145/2133382.2133384openalex-snapshot
When Prefetching Works, When It Doesn’t, and Why
inferred← citeshttps://doi.org/10.1145/3007787.3001184openalex-snapshot
Accelerating dependent cache misses with an enhanced memory controller
inferred← citeshttps://doi.org/10.1201/9781420037425.ch2openalex-snapshot
Performance Modeling and Measurement Techniques
inferred← citeshttps://doi.org/10.1504/ijcaet.2010.029599openalex-snapshot
Multiprocessor simulation using communicating sequential processes
inferred← citeshttps://doi.org/10.15781/t2n58cp64openalex-snapshot
On-Chip Mechanisms to Reduce Effective Memory Access Latency
inferred← citeshttps://doi.org/10.2200/s00273ed1v01y201006cac010openalex-snapshot
Computer Architecture Performance Evaluation Methods
inferred← citeshttps://doi.org/10.5555/1025127.1026003openalex-snapshot
AC/DC: An Adaptive Data Cache Prefetcher
inferred← citeshttps://doi.org/10.5555/2492708.2492825openalex-snapshot
S/DC: a storage and energy efficient data prefetcher
inferred← citeshttps://doi.org/10.5821/dissertation-2117-106295openalex-snapshot
Improving prefetching mechanisms for tiled CMP platforms
inferred← citeshttps://doi.org/10.5821/dissertation-2117-93339openalex-snapshot
Affordable kilo-instruction processors
inferred← citeshttps://doi.org/10.70675/9ef6df79z6dc0z496fzbf8fz99ad6cb42092openalex-snapshot
Processor design-space exploration through fast simulation
inferred← citeshttps://doi.org/10.70675/ca3f8996z3f77z44f3zaad4z9695383b3ca8openalex-snapshot
Accurate Simulation of Data Movement in Modern Mobile Multicore Systems
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.