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Low-Cost Epoch-Based Correlation Prefetching for Commercial Applications
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-58429-3_41openalex-snapshot
The Reliable Router: A reliable and high-performance communication substrate for parallel computers
inferredcites →https://doi.org/10.1007/b117406openalex-snapshot
Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits
inferredcites →https://doi.org/10.1016/0378-4754(92)90033-dopenalex-snapshot
Reliable computer systems — design and evaluation
inferredcites →https://doi.org/10.1109/12.381947openalex-snapshot
Effective hardware-based data prefetching for high-performance processors
inferredcites →https://doi.org/10.1109/12.677221openalex-snapshot
A performance study of instruction cache prefetching methods
inferredcites →https://doi.org/10.1109/24.914544openalex-snapshot
Software-implemented EDAC protection against SEUs
inferredcites →https://doi.org/10.1109/c-m.1978.218016openalex-snapshot
Sequential Program Prefetching in Memory Hierarchies
inferredcites →https://doi.org/10.1109/cgo.2005.34openalex-snapshot
SWIFT: Software Implemented Fault Tolerance
inferredcites →https://doi.org/10.1109/dsn.2004.1311876openalex-snapshot
Tolerating hard faults in microprocessor array structures
inferredcites →https://doi.org/10.1109/dsn.2004.1311888openalex-snapshot
The impact of technology scaling on lifetime reliability
inferredcites →https://doi.org/10.1109/fpt.2005.1568553openalex-snapshot
Post-silicon debug using programmable logic cores
inferredcites →https://doi.org/10.1109/hpca.1996.501191openalex-snapshot
Distributed prefetch-buffer/cache design for high performance memory systems
inferredcites →https://doi.org/10.1109/hpca.2001.903272openalex-snapshot
Reducing DRAM latencies with an integrated memory hierarchy design
inferredcites →https://doi.org/10.1109/hpca.2004.10030openalex-snapshot
Data Cache Prefetching Using a Global History Buffer
inferredcites →https://doi.org/10.1109/hpca.2005.13openalex-snapshot
Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications
inferredcites →https://doi.org/10.1109/hpca.2006.1598108openalex-snapshot
BulletProof: A Defect~Tolerant CMP Switch Architecture
inferredcites →https://doi.org/10.1109/hpca.2006.1598129openalex-snapshot
ReViveI/O: Efficient Handling of I/O in Highly-Available Rollback-Recovery Servers
inferredcites →https://doi.org/10.1109/iccd.2012.6378613openalex-snapshot
Exploiting microarchitectural redundancy for defect tolerance
inferredcites →https://doi.org/10.1109/isca.1990.134547openalex-snapshot
Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
inferredcites →https://doi.org/10.1109/isca.1994.288164openalex-snapshot
Evaluating stream buffers as a secondary cache replacement
inferredcites →https://doi.org/10.1109/isca.1998.694758openalex-snapshot
Memory system characterization of commercial workloads
inferredcites →https://doi.org/10.1109/isca.1998.694759openalex-snapshot
Performance characterization of a quad Pentium Pro SMP using OLTP workloads
inferredcites →https://doi.org/10.1109/isca.1998.694761openalex-snapshot
An analysis of database workload performance on simultaneous multithreaded processors
inferredcites →https://doi.org/10.1109/isca.1998.694794openalex-snapshot
Exploiting spatial locality in data caches using spatial footprints
inferredcites →https://doi.org/10.1109/isca.1998.694797openalex-snapshot
Analytic evaluation of shared-memory systems with ILP processors
inferredcites →https://doi.org/10.1109/isca.2002.1003576openalex-snapshot
Using a user-level memory thread for correlation prefetching
inferredcites →https://doi.org/10.1109/isca.2005.50openalex-snapshot
Temporal Streaming of Shared Memory
inferredcites →https://doi.org/10.1109/ispass.2007.363741openalex-snapshot
Last-Touch Correlated Data Streaming
inferredcites →https://doi.org/10.1109/mascots.2005.12openalex-snapshot
Accurate Modeling of Aggressive Speculation in Modern Microprocessor Architectures
inferredcites →https://doi.org/10.1109/mc.2005.70openalex-snapshot
Robust system design with built-in soft-error resilience
inferredcites →https://doi.org/10.1109/micro.1992.697004openalex-snapshot
Stride Directed Prefetching In Scalar Processors
inferredcites →https://doi.org/10.1109/micro.2003.1253191openalex-snapshot
Scaling and characterizing database workloads: bridging the gap between research and practice
inferredcites →https://doi.org/10.1109/micro.2003.1253245openalex-snapshot
Reducing design complexity of the load/store queue
inferredcites →https://doi.org/10.1109/micro.2004.25openalex-snapshot
MicroLib: A Case for the Quantitative Comparison of Micro-Architecture Mechanisms
inferredcites →https://doi.org/10.1109/micro.2005.31openalex-snapshot
Store Memory-Level Parallelism Optimizations for Commercial Applications
inferredcites →https://doi.org/10.1109/micro.2005.8openalex-snapshot
A Mechanism for Online Diagnosis of Hard Faults in Microprocessors
inferredcites →https://doi.org/10.1109/relphy.2006.251187openalex-snapshot
Prediction of Logic Product Failure Due To Thin-Gate Oxide Breakdown
inferredcites →https://doi.org/10.1109/test.1999.805622openalex-snapshot
The test and debug features of the AMD-K7/sup TM/ microprocessor
inferredcites →https://doi.org/10.1109/test.2000.894222openalex-snapshot
Stuck-fault tests vs. actual defects
inferredcites →https://doi.org/10.1109/test.2000.894227openalex-snapshot
Selection of potentially testable path delay faults for test generation
inferredcites →https://doi.org/10.1109/test.2002.1041810openalex-snapshot
FRITS - a microprocessor functional BIST method
inferredcites →https://doi.org/10.1109/tse.1976.233801openalex-snapshot
Dynamic Improvement of Locality in Virtual Memory Systems
inferredcites →https://doi.org/10.1109/vts.2006.34openalex-snapshot
Evaluation of Test Metrics: Stuck-at, Bridge Coverage Estimate and Gate Exhaustive
inferredcites →https://doi.org/10.1126/science.280.5370.1716openalex-snapshot
A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology
inferredcites →https://doi.org/10.1145/1028176.1006708openalex-snapshot
Microarchitecture Optimizations for Exploiting Memory-Level Parallelism
inferredcites →https://doi.org/10.1145/1168857.1168868openalex-snapshot
Ultra low-cost defect protection for microprocessor pipelines
inferredcites →https://doi.org/10.1145/1189256.1189258openalex-snapshot
Speculative execution in a distributed file system
inferredcites →https://doi.org/10.1145/360128.360135openalex-snapshot
Predictor-directed stream buffers
inferredcites →https://doi.org/10.1145/379240.379259openalex-snapshot
Dead-block prediction & dead-block correlating prefetchers
inferredcites →https://doi.org/10.1145/859618.859621openalex-snapshot
Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor
inferredcites →https://doi.org/10.1145/945506.945509openalex-snapshot
Call graph prefetching for database applications
inferredcites →https://doi.org/10.1145/996566.996588openalex-snapshot
Design and reliability challenges in nanometer technologies
inferredcites →https://doi.org/10.5555/320080.320085openalex-snapshot
Fetch directed instruction prefetching
inferredcites →https://doi.org/10.5555/956417.956571openalex-snapshot
Razor: a low-power pipeline based on circuit-level timing speculation
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Review on data replication strategies in single vs. interconnected cloud systems: Focus on data correlation‐aware strategies
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Fault Tolerant Computer Architecture
inferred← citeshttps://doi.org/10.1007/978-3-031-01743-8openalex-snapshot
A Primer on Hardware Prefetching
inferred← citeshttps://doi.org/10.1007/978-3-319-31596-6_10openalex-snapshot
Online Software-Based Self-Testing in the Dark Silicon Era
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Characterizing and Understanding the Bandwidth Behavior of Workloads on Multi-core Processors
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Simple Operations in Memory to Reduce Data Movement
inferred← citeshttps://doi.org/10.1016/bs.adcom.2021.11.006openalex-snapshot
Beyond spatial or temporal prefetching
inferred← citeshttps://doi.org/10.1016/j.parco.2012.06.002openalex-snapshot
Algorithm-level Feedback-controlled Adaptive data prefetcher: Accelerating data access for high-performance processors
inferred← citeshttps://doi.org/10.1016/j.vlsi.2018.04.015openalex-snapshot
Low overhead online periodic testing for GPGPUs
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An Online Mechanism to Verify Datapath Execution Using Existing Resources in Chip Multiprocessors
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Architectures for online error detection and recovery in multicore processors
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REPAIR: Hard-error recovery via re-execution
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Trace-based microarchitecture-level diagnosis of permanent hardware faults
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Detouring: Translating software to circumvent hard faults in simple cores
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Emμcode: Masking hard faults in complex functional units
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Hardware-Software Integrated Diagnosis for Intermittent Hardware Faults
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Cardio: Adaptive CMPs for reliability through dynamic introspective operation
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Voltage emergency prediction: Using signatures to reduce operating margins
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Practical off-chip meta-data for temporal memory streaming
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Accurate microarchitecture-level fault modeling for studying hardware faults
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Understanding the impact of gate-level physical reliability effects on whole program execution
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Best-offset hardware prefetching
inferred← citeshttps://doi.org/10.1109/hpca.2018.00021openalex-snapshot
Domino Temporal Data Prefetcher
inferred← citeshttps://doi.org/10.1109/hpca.2019.00053openalex-snapshot
Bingo Spatial Data Prefetcher
inferred← citeshttps://doi.org/10.1109/hpca57654.2024.00040openalex-snapshot
Differential-Matching Prefetcher for Indirect Memory Access
inferred← citeshttps://doi.org/10.1109/hpca68181.2026.11408449openalex-snapshot
Athena: Synergizing Data Prefetching and Off-Chip Prediction via Online Reinforcement Learning
inferred← citeshttps://doi.org/10.1109/iccd.2008.4751935openalex-snapshot
Exploiting producer patterns and L2 cache for timely dependence-based prefetching
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Adaptive online testing for efficient hard fault detection
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Energy optimal on-line Self-Test of microprocessors in WSN nodes
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Temporal streams in commercial server applications
inferred← citeshttps://doi.org/10.1109/ijcnn55064.2022.9892198openalex-snapshot
Towards the Design of Efficient TCN-bascd Prefetcher for Hybrid NVM-DRAM Memory
inferred← citeshttps://doi.org/10.1109/iolts.2008.15openalex-snapshot
On-Line Failure Detection and Confinement in Caches
inferred← citeshttps://doi.org/10.1109/iolts.2008.18openalex-snapshot
Directed Random SBST Generation for On-Line Testing of Pipelined Processors
inferred← citeshttps://doi.org/10.1109/iolts.2010.5560233openalex-snapshot
SBST for on-line detection of hard faults in multiprocessor applications under energy constraints
inferred← citeshttps://doi.org/10.1109/ipdps.2012.68openalex-snapshot
Miss-Correlation Folding: Encoding Per-Block Miss Correlations in Compressed DRAM for Data Prefetching
inferred← citeshttps://doi.org/10.1109/irps.2011.5784500openalex-snapshot
Reliability- and Process-variation aware design of integrated circuits — A broader perspective
inferred← citeshttps://doi.org/10.1109/isca59077.2024.00017openalex-snapshot
Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution
inferred← citeshttps://doi.org/10.1109/isca59077.2024.00088openalex-snapshot
A New Formulation of Neural Data Prefetching
inferred← citeshttps://doi.org/10.1109/isca59077.2024.00090openalex-snapshot
Triangel: A High-Performance, Accurate, Timely On-Chip Temporal Prefetcher
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Parameter Variation Tolerance and Error Resiliency: New Design Paradigm for the Nanoscale Era
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Exploring the Interaction Between Device Lifetime Reliability and Security Vulnerabilities
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DCC: A Dependable Cache Coherence Multicore Architecture
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Harnessing Pairwise-Correlating Data Prefetching With Runahead Metadata
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Self-Test and Diagnosis for Self-Aware Systems
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Reliable Systems on Unreliable Fabrics
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Temporal instruction fetch streaming
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The StageNet fabric for constructing resilient multicore systems
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Online design bug detection: RTL analysis, flexible mechanisms, and evaluation
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Error Correlation Prediction in Lockstep Processors for Safety-Critical Systems
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Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction
inferred← citeshttps://doi.org/10.1109/mm.2010.21openalex-snapshot
Making Address-Correlated Prefetching Practical
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A General, Fault tolerant, Adaptive, Deadlock-free Routing Protocol for Network-on-chip
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Combining Error Detection and Transactional Memory for Energy-Efficient Computing below Safe Operation Margins
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COMeT: Continuous Online Memory Test
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Cobra: A comprehensive bundle-based reliable architecture
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Application data prefetching on the IBM Blue Gene/Q supercomputer
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A Software Solution for Hardware Vulnerabilities
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Generic construction of monitors for Floating Point Unit designs
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Software-Based Self-Testing of Symmetric Shared-Memory Multiprocessors
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Microarchitectural Online Testing for Failure Detection in Memory Order Buffers
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A Flexible Software-Based Framework for Online Detection of Hardware Defects
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Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors
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Implementing End-to-End Register Data-Flow Continuous Self-Test
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Practical Temporal Prefetching With Compressed On-Chip Metadata
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Instruction-Based Online Periodic Self-Testing of Microprocessors with Floating-Point Units
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Hardware/Software Codesign Architecture for Online Testing in Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/test.2008.4700582openalex-snapshot
On-line Failure Detection in Memory Order Buffers
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VAST: Virtualization-Assisted Concurrent Autonomous Self-Test
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Shadow checker (SC): A low-cost hardware scheme for online detection of faults in small memory structures of a microprocessor
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Self-repair of uncore components in robust system-on-chips: An OpenSPARC T2 case study
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Characterizing the Impact of Intermittent Hardware Faults on Programs
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Area Efficient ROM-Embedded SRAM Cache
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Concurrent autonomous self-test for uncore components in system-on-chips
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Understanding the propagation of hard errors to software and implications for resilient system design
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Understanding the propagation of hard errors to software and implications for resilient system design
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Understanding the propagation of hard errors to software and implications for resilient system design
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Understanding the propagation of hard errors to software and implications for resilient system design
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Architectural core salvaging in a multi-core processor for hard-error tolerance
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Architectural core salvaging in a multi-core processor for hard-error tolerance
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Operating system scheduling for efficient online self-test in robust systems
inferred← citeshttps://doi.org/10.1145/1837274.1837407openalex-snapshot
Using introspective software-based testing for post-silicon debug and repair
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Exploring circuit timing-aware language and compilation
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Exploring circuit timing-aware language and compilation
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Exploring circuit timing-aware language and compilation
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Reliable on-chip systems in the nano-era
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A survey of checker architectures
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Fault resilient physical neural networks on a single chip
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Hardware Fault Recovery for I/O Intensive Applications
inferred← citeshttps://doi.org/10.1145/2738052openalex-snapshot
Reliable Integrity Checking in Multicore Processors
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A Low-Overhead, Fully-Distributed, Guaranteed-Delivery Routing Algorithm for Faulty Network-on-Chips
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Identifying Security Critical Properties for the Dynamic Verification of a Processor
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Evaluation of Hardware Data Prefetchers on Server Processors
inferred← citeshttps://doi.org/10.1145/3352460.3358300openalex-snapshot
Temporal Prefetching Without the Off-Chip Metadata
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Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning
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MetaSys: A Practical Open-source Metadata Management System to Implement and Evaluate Cross-layer Optimizations
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ABMLP: Attention-Based Multi-Layer Perceptron Prefetcher
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Hyperion: A Highly Effective Page and PC Based Delta Prefetcher
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Garibaldi: A Pairwise Instruction-Data Management for Enhancing Shared Last-Level Cache Performance in Server Workloads
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Prefetching Scheme for Massive Spatiotemporal Data in a Smart City
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Power Laws na modelagem de caches de microprocessadores.
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Integrated hardware-software diagnosis of intermittent faults
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DMDP: A Dynamic Multi-Delta Prefetcher with Customizable Runtime Quality-Aware Feedback
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A Primer on Hardware Prefetching
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SOFTWARE SUPPORT FOR HARDWARE PREDICTORS
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High Throughput Memory with Silicon Photonics in Chiplet-based Architectures for Irregular Workloads
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The Processing Using Memory Paradigm:In-DRAM Bulk Copy, Initialization, Bitwise AND and OR
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Design techniques for cross-layer resilience
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Application data prefetching on the IBM blue gene/Q supercomputer
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Power-aware online testing of manycore systems in the dark silicon era
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Conception d'un micro-réseau intégré NOC tolérant les fautes multiples statiques et dynamiques
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