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Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns

https://doi.org/10.1109/micro.2005.11
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/hpca.2000.824351openalex-snapshot
A prefetching technique for irregular accesses to linked data structures
inferredcites →https://doi.org/10.1109/hpca.2003.1183532openalex-snapshot
Runahead execution: an alternative to very large instruction windows for out-of-order processors
inferredcites →https://doi.org/10.1109/hpca.2005.9openalex-snapshot
Checkpointed early load retirement
inferredcites →https://doi.org/10.1109/isca.1999.765939openalex-snapshot
Correlated load-address predictors
inferredcites →https://doi.org/10.1109/isca.1999.765944openalex-snapshot
Effective jump-pointer prefetching for linked data structures
inferredcites →https://doi.org/10.1109/isca.2002.1003559openalex-snapshot
Increasing processor performance by implementing deeper pipelines
inferredcites →https://doi.org/10.1109/isca.2005.49openalex-snapshot
Techniques for Efficient Processing in Runahead Execution Engines
inferredcites →https://doi.org/10.1109/l-ca.2002.8openalex-snapshot
MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research
inferredcites →https://doi.org/10.1109/l-ca.2004.3openalex-snapshot
CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction
inferredcites →https://doi.org/10.1109/micro.1995.476830openalex-snapshot
SPAID: software prefetching in pointer- and call-intensive environments
inferredcites →https://doi.org/10.1109/micro.1997.645815openalex-snapshot
The predictability of data values
inferredcites →https://doi.org/10.1109/micro.1997.645819openalex-snapshot
Highly accurate data value prediction using hybrid predictors
inferredcites →https://doi.org/10.1109/micro.2002.1176239openalex-snapshot
Pointer cache assisted prefetching
inferredcites →https://doi.org/10.1109/mm.2003.1261383openalex-snapshot
Runahead execution: an effective alternative to large instruction windows
inferredcites →https://doi.org/10.1109/tc.2005.117openalex-snapshot
Enhancing Memory-Level Parallelism via Recovery-Free Value Prediction
inferredcites →https://doi.org/10.1145/1028176.1006708openalex-snapshot
Microarchitecture Optimizations for Exploiting Memory-Level Parallelism
inferredcites →https://doi.org/10.1145/1080695.1070000openalex-snapshot
Techniques for Efficient Processing in Runahead Execution Engines
inferredcites →https://doi.org/10.1145/201059.201065openalex-snapshot
Supporting dynamic data structures on distributed-memory machines
inferredcites →https://doi.org/10.1145/216585.216588openalex-snapshot
Hitting the memory wall
inferredcites →https://doi.org/10.1145/237090.237173openalex-snapshot
Value locality and load value prediction
inferredcites →https://doi.org/10.1145/237090.237190openalex-snapshot
Compiler-based prefetching for recursive data structures
inferredcites →https://doi.org/10.1145/2591635.2667173openalex-snapshot
Improving data cache performance by pre-executing instructions under a cache miss
inferredcites →https://doi.org/10.1145/263580.263597openalex-snapshot
Improving data cache performance by pre-executing instructions under a cache miss
inferredcites →https://doi.org/10.1145/264107.264207openalex-snapshot
Prefetching using Markov predictors
inferredcites →https://doi.org/10.1145/277044.277226openalex-snapshot
Power considerations in the design of the Alpha 21264 microprocessor
inferredcites →https://doi.org/10.1145/291069.291034openalex-snapshot
Dependence based prefetching for linked data structures
inferredcites →https://doi.org/10.1145/300979.300984openalex-snapshot
Correlated load-address predictors
inferredcites →https://doi.org/10.1145/300979.300989openalex-snapshot
Effective jump-pointer prefetching for linked data structures
inferredcites →https://doi.org/10.1145/335231.335248openalex-snapshot
Push vs. pull
inferredcites →https://doi.org/10.1145/373574.373576openalex-snapshot
The memory gap and the future of high performance memories
inferredcites →https://doi.org/10.1145/545214.545219openalex-snapshot
Increasing processor performance by implementing deeper pipelines
inferredcites →https://doi.org/10.1145/605397.605403openalex-snapshot
Automatically characterizing large scale program behavior
inferredcites →https://doi.org/10.1145/605397.605427openalex-snapshot
A stateless, content-directed data prefetching mechanism
inferredcites →https://doi.org/10.1145/782814.782859openalex-snapshot
Enhancing memory level parallelism via recovery-free value prediction
inferredcites →https://doi.org/10.1147/rd.374.0547openalex-snapshot
A load-instruction unit for pipelined processors
inferredcites →https://doi.org/10.5555/225160.225197openalex-snapshot
SPAID: software prefetching in pointer- and call-intensive environments
inferredcites →https://doi.org/10.5555/266800.266824openalex-snapshot
The predictability of data values
inferredcites →https://doi.org/10.5555/266800.266827openalex-snapshot
Highly accurate data value prediction using hybrid predictors
inferredcites →https://doi.org/10.5555/774861.774869openalex-snapshot
Pointer cache assisted prefetching

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Optimization of OLAP In-Memory Database Management Systems with Processing-In-Memory Architecture
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The Processing-in-Memory Paradigm: Mechanisms to Enable Adoption
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Towards Breaking the Memory Bandwidth Wall Using Approximate Value Prediction
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Techniques for bandwidth-efficient prefetching of linked data structures in hybrid prefetching systems
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ChargeCache: Reducing DRAM latency by exploiting row access locality
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Domino Temporal Data Prefetcher
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Precise Runahead Execution
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Differential-Matching Prefetcher for Indirect Memory Access
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Athena: Synergizing Data Prefetching and Off-Chip Prediction via Online Reinforcement Learning
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Reducing register file size through instruction pre-execution enhanced by value prediction
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Accelerating pointer chasing in 3D-stacked memory: Challenges, mechanisms, evaluation
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Accelerating Dependent Cache Misses with an Enhanced Memory Controller
inferred← citeshttps://doi.org/10.1109/isca52012.2021.00024openalex-snapshot
Vector Runahead
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Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution
inferred← citeshttps://doi.org/10.1109/isca66397.2026.00053openalex-snapshot
Revisiting Global Value Prediction: A Resurgent Complement to Local Predictors
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Mitigating the Memory Bottleneck With Approximate Load Value Prediction
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A performance-correctness explicitly-decoupled architecture
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Loop-Aware Memory Prefetching Using Code Block Working Sets
inferred← citeshttps://doi.org/10.1109/micro.2016.7783764openalex-snapshot
Continuous runahead: Transparent hardware acceleration for memory intensive workloads
inferred← citeshttps://doi.org/10.1109/mm.2006.10openalex-snapshot
Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance
inferred← citeshttps://doi.org/10.1109/pact52795.2021.00025openalex-snapshot
Write Prediction for Persistent Memory Systems
inferred← citeshttps://doi.org/10.1109/tc.2006.191openalex-snapshot
Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses
inferred← citeshttps://doi.org/10.1109/tpds.2007.1080openalex-snapshot
Submitted to IEEE Transactions on Parallel and Distributed Systems Special Issue on CMP Architectures
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Optimizing Dual-Core Execution for Power Efficiency and Transient-Fault Recovery
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Kilo-instruction processors, runahead and prefetching
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Data prefetching and address pre-calculation through instruction pre-execution with two-step physical register deallocation
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Hiding the misprediction penalty of a resource-efficient high-performance processor
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RFVP
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Accelerating dependent cache misses with an enhanced memory controller
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Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning
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Research Problems and Opportunities in Memory Systems
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Register File Size Reduction through Instruction Pre-Execution Incorporating Value Prediction
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Prefetching for complex memory access patterns
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Adaptive-Latency DRAM (AL-DRAM)
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Reducing DRAM Access Latency by Exploiting DRAM Leakage Characteristics and Common Access Patterns
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High-Performance and Energy-Effcient Memory Scheduler Design for Heterogeneous Systems
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Exploiting the DRAM Microarchitecture to Increase Memory-Level Parallelism
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Exploiting Row-Level Temporal Locality in DRAM to Reduce the Memory Access Latency
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