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Enhancing memory level parallelism via recovery-free value prediction

https://doi.org/10.1145/782814.782859
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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/12.752653openalex-snapshot
Prefetching using Markov predictors
inferredcites →https://doi.org/10.1109/2.869367openalex-snapshot
SPEC CPU2000: measuring CPU performance in the New Millennium
inferredcites →https://doi.org/10.1109/40.491460openalex-snapshot
The Mips R10000 superscalar microprocessor
inferredcites →https://doi.org/10.1109/hpca.2001.903250openalex-snapshot
Speculative data-driven multithreading
inferredcites →https://doi.org/10.1109/hpca.2002.995709openalex-snapshot
Memory latency-tolerance approaches for Itanium processors: out-of-order execution vs. speculative precomputation
inferredcites →https://doi.org/10.1109/hpca.2003.1183532openalex-snapshot
Runahead execution: an alternative to very large instruction windows for out-of-order processors
inferredcites →https://doi.org/10.1145/237090.237173openalex-snapshot
Value locality and load value prediction
inferredcites →https://doi.org/10.1145/2591635.2667173openalex-snapshot
Improving data cache performance by pre-executing instructions under a cache miss
inferredcites →https://doi.org/10.1145/263580.263597openalex-snapshot
Improving data cache performance by pre-executing instructions under a cache miss
inferredcites →https://doi.org/10.1145/263580.263631openalex-snapshot
Speculative execution via address prediction and data prefetching
inferredcites →https://doi.org/10.1145/268806.268810openalex-snapshot
The SimpleScalar tool set, version 2.0
inferredcites →https://doi.org/10.1145/300979.300984openalex-snapshot
Correlated load-address predictors
inferredcites →https://doi.org/10.1145/379240.379246openalex-snapshot
Execution-based prediction using speculative slices
inferredcites →https://doi.org/10.1145/379240.379248openalex-snapshot
Speculative precomputation
inferredcites →https://doi.org/10.1145/379240.379250openalex-snapshot
Tolerating memory latency through software-controlled pre-execution in simultaneous multithreading processors
inferredcites →https://doi.org/10.1145/512529.512555openalex-snapshot
Efficient discovery of regular stride patterns in irregular programs and its use in compiler prefetching
inferredcites →https://doi.org/10.1145/545214.545219openalex-snapshot
Increasing processor performance by implementing deeper pipelines
inferredcites →https://doi.org/10.1145/545214.545223openalex-snapshot
A large, fast instruction window for tolerating cache misses
inferredcites →https://doi.org/10.1145/605397.605427openalex-snapshot
A stateless, content-directed data prefetching mechanism
inferredcites →https://doi.org/10.1145/859618.859656openalex-snapshot
Detecting global stride locality in value streams
inferredcites →https://doi.org/10.5555/255235.255275openalex-snapshot
Predictability of load/store instruction latencies
inferredcites →https://doi.org/10.5555/266800.266824openalex-snapshot
The predictability of data values
inferredcites →https://doi.org/10.5555/266800.266827openalex-snapshot
Highly accurate data value prediction using hybrid predictors
inferredcites →https://doi.org/10.5555/320080.320086openalex-snapshot
Improving branch predictors by correlating on data values
inferredcites →https://doi.org/10.5555/517554.825771openalex-snapshot
On Some Implementation Issues for Value Prediction on Wide-Issue ILP Processors
inferredcites →https://doi.org/10.5555/520793.825756openalex-snapshot
Control-flow speculation through value prediction for superscalar processors

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1002/ecj.10424openalex-snapshot
A stride value predictor suppressing conflicts focusing on predictability
inferred← citeshttps://doi.org/10.1109/date.2010.5457197openalex-snapshot
Energy-performance design space exploration in SMT architectures exploiting selective load value predictions
inferred← citeshttps://doi.org/10.1109/hpca.2005.9openalex-snapshot
Checkpointed early load retirement
inferred← citeshttps://doi.org/10.1109/hpca.2007.346201openalex-snapshot
A Memory-Level Parallelism Aware Fetch Policy for SMT Processors
inferred← citeshttps://doi.org/10.1109/hpcasia.2005.82openalex-snapshot
Queue usage and memory-level parallelism sensitive scheduling
inferred← citeshttps://doi.org/10.1109/iccd.2009.5413149openalex-snapshot
Reducing register file size through instruction pre-execution enhanced by value prediction
inferred← citeshttps://doi.org/10.1109/iccsn.2011.6013954openalex-snapshot
How many entries we need in miss handling architectures of L1 and L2 cache?
inferred← citeshttps://doi.org/10.1109/isca.2004.1310765openalex-snapshot
Microarchitecture optimizations for exploiting memory-level parallelism
inferred← citeshttps://doi.org/10.1109/l-ca.2004.3openalex-snapshot
CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction
inferred← citeshttps://doi.org/10.1109/micro.2005.11openalex-snapshot
Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns
inferred← citeshttps://doi.org/10.1109/micro.2005.28openalex-snapshot
ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing
inferred← citeshttps://doi.org/10.1109/micro.2006.44openalex-snapshot
Scalable Cache Miss Handling for High Memory-Level Parallelism
inferred← citeshttps://doi.org/10.1109/pact.2005.18openalex-snapshot
Dual-core execution: building a highly scalable single-thread instruction window
inferred← citeshttps://doi.org/10.1109/pact.2005.23openalex-snapshot
Future execution: a hardware prefetching technique for chip multiprocessors
inferred← citeshttps://doi.org/10.1109/tc.2005.117openalex-snapshot
Enhancing Memory-Level Parallelism via Recovery-Free Value Prediction
inferred← citeshttps://doi.org/10.1109/tc.2006.191openalex-snapshot
Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses
inferred← citeshttps://doi.org/10.1145/1028176.1006708openalex-snapshot
Microarchitecture Optimizations for Exploiting Memory-Level Parallelism
inferred← citeshttps://doi.org/10.1145/1138035.1138036openalex-snapshot
A lifetime optimal algorithm for speculative PRE
inferred← citeshttps://doi.org/10.1145/1138035.1138038openalex-snapshot
CAVA
inferred← citeshttps://doi.org/10.1145/1150019.1136501openalex-snapshot
A Case for MLP-Aware Cache Replacement
inferred← citeshttps://doi.org/10.1145/1187976.1187979openalex-snapshot
Future execution
inferred← citeshttps://doi.org/10.1145/1242531.1242536openalex-snapshot
An analysis of the effects of miss clustering on the cost of a cache miss
inferred← citeshttps://doi.org/10.1145/1281700.1281715openalex-snapshot
Pipeline spectroscopy
inferred← citeshttps://doi.org/10.1145/1509864.1509867openalex-snapshot
Memory-level parallelism aware fetch policies for simultaneous multithreading processors
inferred← citeshttps://doi.org/10.1145/1669112.1669155openalex-snapshot
Improving memory bank-level parallelism in the presence of prefetching
inferred← citeshttps://doi.org/10.1145/2086696.2086707openalex-snapshot
Efficiently exploiting memory level parallelism on asymmetric coupled cores in the dark silicon era
inferred← citeshttps://doi.org/10.1145/2628071.2628110openalex-snapshot
Rollback-free value prediction with approximate loads
inferred← citeshttps://doi.org/10.1184/r1/6469421openalex-snapshot
The Main Memory System: Challenges and Opportunities
inferred← citeshttps://doi.org/10.14529/jsfi140302openalex-snapshot
Research Problems and Opportunities in Memory Systems
inferred← citeshttps://doi.org/10.1541/ieejeiss.131.1260openalex-snapshot
A Stride Value Predictor Suppressing Conflicts Focusing on Predictability
inferred← citeshttps://doi.org/10.1541/ieejeiss.132.1706openalex-snapshot
Energy Saving of Value Prediction by Expanding Branch Target Buffer
inferred← citeshttps://doi.org/10.15623/ijret.2014.0307079openalex-snapshot
HARDBACK SOLUTION TO ACCELERATE MULTIMEDIA COMPUTATION THROUGH MGP IN CMP
inferred← citeshttps://doi.org/10.1587/transinf.e93.d.3294openalex-snapshot
Register File Size Reduction through Instruction Pre-Execution Incorporating Value Prediction
inferred← citeshttps://doi.org/10.5121/ijcsit.2016.8605openalex-snapshot
Reducing Competitive Cache Misses in Modern Processor Architectures
inferred← citeshttps://doi.org/10.5555/1870926.1870992openalex-snapshot
Energy-performance design space exploration in SMT architectures exploiting selective load value predictions
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