On the public citation graph
Loop-Aware Memory Prefetching Using Code Block Working Sets
0 signed · 56 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1109/cgo.2004.1281665openalex-snapshot
LLVM: a compilation framework for lifelong program analysis & transformation
inferredcites →https://doi.org/10.1109/hpca.2003.1183532openalex-snapshot
Runahead execution: an alternative to very large instruction windows for out-of-order processors
inferredcites →https://doi.org/10.1109/hpca.2004.10030openalex-snapshot
Data Cache Prefetching Using a Global History Buffer
inferredcites →https://doi.org/10.1109/hpca.2007.346185openalex-snapshot
Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers
inferredcites →https://doi.org/10.1109/hpca.2009.4798232openalex-snapshot
Techniques for bandwidth-efficient prefetching of linked data structures in hybrid prefetching systems
inferredcites →https://doi.org/10.1109/hpca.2011.5749728openalex-snapshot
Fast thread migration via cache working set prediction
inferredcites →https://doi.org/10.1109/hpca.2013.6522309openalex-snapshot
RECAP: A region-based cure for the common cold (cache)
inferredcites →https://doi.org/10.1109/iiswc.2009.5306797openalex-snapshot
Rodinia: A benchmark suite for heterogeneous computing
inferredcites →https://doi.org/10.1109/isca.1994.288164openalex-snapshot
Evaluating stream buffers as a secondary cache replacement
inferredcites →https://doi.org/10.1109/isca.1995.524546openalex-snapshot
The SPLASH-2 programs: characterization and methodological considerations
inferredcites →https://doi.org/10.1109/l-ca.2011.33openalex-snapshot
B-Fetch: Branch Prediction Directed Prefetching for In-Order Processors
inferredcites →https://doi.org/10.1109/micro.1992.697004openalex-snapshot
Stride Directed Prefetching In Scalar Processors
inferredcites →https://doi.org/10.1109/micro.2005.11openalex-snapshot
Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns
inferredcites →https://doi.org/10.1109/pact.2004.1342548openalex-snapshot
AC/DC: an adaptive data cache prefetcher
inferredcites →https://doi.org/10.1145/1006209.1006211openalex-snapshot
Effective stream-based and execution-based data prefetching
inferredcites →https://doi.org/10.1145/123465.123475openalex-snapshot
Two-level adaptive training branch prediction
inferredcites →https://doi.org/10.1145/144965.145006openalex-snapshot
Stride directed prefetching in scalar processors
inferredcites →https://doi.org/10.1145/1555754.1555766openalex-snapshot
Spatio-temporal memory streaming
inferredcites →https://doi.org/10.1145/191995.192014openalex-snapshot
Evaluating stream buffers as a secondary cache replacement
inferredcites →https://doi.org/10.1145/1950365.1950411openalex-snapshot
Inter-core prefetching for multicore processors using migrating helper threads
inferredcites →https://doi.org/10.1145/1961295.1950411openalex-snapshot
Inter-core prefetching for multicore processors using migrating helper threads
inferredcites →https://doi.org/10.1145/2133382.2133384openalex-snapshot
When Prefetching Works, When It Doesn’t, and Why
inferredcites →https://doi.org/10.1145/2370816.2370886openalex-snapshot
Application-aware prefetch prioritization in on-chip networks
inferredcites →https://doi.org/10.1145/2464996.2465014openalex-snapshot
Diagnosis and optimization of application prefetching performance
inferredcites →https://doi.org/10.1145/264107.264207openalex-snapshot
Prefetching using Markov predictors
inferredcites →https://doi.org/10.1145/285930.285998openalex-snapshot
Improving direct-mapped cache performance by the addition of a small fully-associative cache prefetch buffers
inferredcites →https://doi.org/10.1145/325096.325162openalex-snapshot
Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
inferredcites →https://doi.org/10.5555/1025127.1026003openalex-snapshot
AC/DC: An Adaptive Data Cache Prefetcher
inferredcites →https://doi.org/10.5555/320080.320085openalex-snapshot
Fetch directed instruction prefetching
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-319-78890-6_8openalex-snapshot
Lookahead Memory Prefetching for CGRAs Using Partial Loop Unrolling
inferred← citeshttps://doi.org/10.1109/hipc.2017.00018openalex-snapshot
Last Level Collective Hardware Prefetching For Data-Parallel Applications
inferred← citeshttps://doi.org/10.1109/hpca.2018.00021openalex-snapshot
Domino Temporal Data Prefetcher
inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00061openalex-snapshot
Prodigy: Improving the Memory Latency of Data-Indirect Irregular Workloads Using Hardware-Software Co-Design
inferred← citeshttps://doi.org/10.1109/hpca57654.2024.00040openalex-snapshot
Differential-Matching Prefetcher for Indirect Memory Access
inferred← citeshttps://doi.org/10.1109/isca.2018.00027openalex-snapshot
A Case for Richer Cross-Layer Abstractions: Bridging the Semantic Gap with Expressive Memory
inferred← citeshttps://doi.org/10.1109/mascots50786.2020.9285963openalex-snapshot
Symbiotic HW Cache and SW DTLB Prefetching for DRAM/NVM Hybrid Memory
inferred← citeshttps://doi.org/10.1109/tcad.2017.2748026openalex-snapshot
CDPM: Context-Directed Pattern Matching Prefetching to Improve Coarse-Grained Reconfigurable Array Performance
inferred← citeshttps://doi.org/10.1145/2897937.2898001openalex-snapshot
Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays
inferred← citeshttps://doi.org/10.1145/2907071openalex-snapshot
A Survey of Recent Prefetching Techniques for Processor Caches
inferred← citeshttps://doi.org/10.1145/2925426.2926254openalex-snapshot
Graph Prefetching Using Data Structure Knowledge
inferred← citeshttps://doi.org/10.1145/3037697.3037705openalex-snapshot
Translation-Triggered Prefetching
inferred← citeshttps://doi.org/10.1145/3093315.3037705openalex-snapshot
Translation-Triggered Prefetching
inferred← citeshttps://doi.org/10.1145/3093336.3037705openalex-snapshot
Translation-Triggered Prefetching
inferred← citeshttps://doi.org/10.1145/3093337.3037705openalex-snapshot
Translation-Triggered Prefetching
inferred← citeshttps://doi.org/10.1145/3419973openalex-snapshot
Highly Concurrent Latency-tolerant Register Files for GPUs
inferred← citeshttps://doi.org/10.1145/3676151.3719375openalex-snapshot
Multi-Strided Access Patterns to Boost Hardware Prefetching
inferred← citeshttps://doi.org/10.1145/3725843.3756031openalex-snapshot
Symbiotic Task Scheduling and Data Prefetching
inferred← citeshttps://doi.org/10.1587/elex.21.20240664openalex-snapshot
Contiguity aware TLB prefetching for embedded I/O devices
inferred← citeshttps://doi.org/10.48550/arxiv.2010.09330openalex-snapshot
Enabling High-Capacity, Latency-Tolerant, and Highly-Concurrent GPU Register Files via Software/Hardware Cooperation
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.