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Store Memory-Level Parallelism Optimizations for Commercial Applications
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-540-30554-5_19openalex-snapshot
Programming Languages and Operating Systems
inferredcites →https://doi.org/10.1109/eurmic.1998.711822openalex-snapshot
Impact of reducing miss write latencies in multiprocessors with two level cache
inferredcites →https://doi.org/10.1109/hpca.2003.1183532openalex-snapshot
Runahead execution: an alternative to very large instruction windows for out-of-order processors
inferredcites →https://doi.org/10.1109/hpca.2005.10openalex-snapshot
Chip Multithreading: Opportunities and Challenges
inferredcites →https://doi.org/10.1109/hpca.2005.13openalex-snapshot
Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications
inferredcites →https://doi.org/10.1109/iccd.1995.528915openalex-snapshot
Write buffer design for cache-coherent shared-memory multiprocessors
inferredcites →https://doi.org/10.1109/isca.1990.134503openalex-snapshot
Memory consistency and event ordering in scalable shared-memory multiprocessors
inferredcites →https://doi.org/10.1109/isca.1993.698560openalex-snapshot
Cache Write Policies And Performance
inferredcites →https://doi.org/10.1109/isca.1998.694758openalex-snapshot
Memory system characterization of commercial workloads
inferredcites →https://doi.org/10.1109/isca.1998.694761openalex-snapshot
An analysis of database workload performance on simultaneous multithreaded processors
inferredcites →https://doi.org/10.1109/isca.1998.694797openalex-snapshot
Analytic evaluation of shared-memory systems with ILP processors
inferredcites →https://doi.org/10.1109/isca.2005.31openalex-snapshot
Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking
inferredcites →https://doi.org/10.1109/isca.2005.42openalex-snapshot
RegionScout: Exploiting Coarse Grain Sharing in Snoop-Based Coherence
inferredcites →https://doi.org/10.1109/isca.2005.46openalex-snapshot
Scalable Load and Store Processing in Latency Tolerant Processors
inferredcites →https://doi.org/10.1109/ispass.2000.842285openalex-snapshot
Issues in the design of store buffers in dynamically scheduled processors
inferredcites →https://doi.org/10.1109/l-ca.2002.11openalex-snapshot
Request Reordering to Enhance the Performance of Strict Consistency Models
inferredcites →https://doi.org/10.1109/mc.2003.1178049openalex-snapshot
Queuing simulation model for multiprocessor systems
inferredcites →https://doi.org/10.1109/micro.2001.991127openalex-snapshot
Speculative lock elision: enabling highly concurrent multithreaded execution
inferredcites →https://doi.org/10.1109/micro.2003.1253191openalex-snapshot
Scaling and characterizing database workloads: bridging the gap between research and practice
inferredcites →https://doi.org/10.1109/micro.2003.1253245openalex-snapshot
Reducing design complexity of the load/store queue
inferredcites →https://doi.org/10.1109/mm.2005.49openalex-snapshot
High-Performance Throughput Computing
inferredcites →https://doi.org/10.1109/tc.1979.1675439openalex-snapshot
How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs
inferredcites →https://doi.org/10.1145/1006209.1006211openalex-snapshot
Effective stream-based and execution-based data prefetching
inferredcites →https://doi.org/10.1145/1028176.1006708openalex-snapshot
Microarchitecture Optimizations for Exploiting Memory-Level Parallelism
inferredcites →https://doi.org/10.1145/1080695.1069991openalex-snapshot
Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking
inferredcites →https://doi.org/10.1145/1080695.1070007openalex-snapshot
Scalable Load and Store Processing in Latency Tolerant Processors
inferredcites →https://doi.org/10.1145/161468.161469openalex-snapshot
A methodology for implementing highly concurrent data objects
inferredcites →https://doi.org/10.1145/165123.165154openalex-snapshot
Cache write policies and performance
inferredcites →https://doi.org/10.1145/17356.17406openalex-snapshot
Memory access buffering in multiprocessors
inferredcites →https://doi.org/10.1145/195473.195524openalex-snapshot
Contrasting characteristics and cache performance of technical and multi-user commercial workloads
inferredcites →https://doi.org/10.1145/258492.258512openalex-snapshot
Using speculative retirement and larger instruction windows to narrow the performance gap between memory consistency models
inferredcites →https://doi.org/10.1145/2591635.2667173openalex-snapshot
Improving data cache performance by pre-executing instructions under a cache miss
inferredcites →https://doi.org/10.1145/263580.263597openalex-snapshot
Improving data cache performance by pre-executing instructions under a cache miss
inferredcites →https://doi.org/10.1145/279358.279363openalex-snapshot
Memory system characterization of commercial workloads
inferredcites →https://doi.org/10.1145/279358.279367openalex-snapshot
An analysis of database workload performance on simultaneous multithreaded processors
inferredcites →https://doi.org/10.1145/279358.279408openalex-snapshot
Analytic evaluation of shared-memory systems with ILP processors
inferredcites →https://doi.org/10.1145/285930.285997openalex-snapshot
Memory consistency and event ordering in scalable shared-memory multiprocessors
inferredcites →https://doi.org/10.1145/291069.291067openalex-snapshot
Performance of database workloads on shared-memory systems with out-of-order processors
inferredcites →https://doi.org/10.1145/68182.68188openalex-snapshot
Efficient synchronization primitives for large-scale cache-coherent multiprocessors
inferredcites →https://doi.org/10.1145/70082.68188openalex-snapshot
Efficient synchronization primitives for large-scale cache-coherent multiprocessors
inferredcites →https://doi.org/10.5555/563998.564036openalex-snapshot
Speculative lock elision: enabling highly concurrent multithreaded execution
inferredcites →https://doi.org/10.5555/956417.956555openalex-snapshot
Reducing design complexity of the load/store queue
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1109/hpca68181.2026.11408509openalex-snapshot
PhasedStore: Supporting High-Performance Write-Through Cache-Coherence Protocols Under TSO
inferred← citeshttps://doi.org/10.1109/isca.2018.00029openalex-snapshot
Dynamic Memory Dependence Predication
inferred← citeshttps://doi.org/10.1109/mascots.2018.00022openalex-snapshot
Quantifying and Optimizing Data Access Parallelism on Manycores
inferred← citeshttps://doi.org/10.1109/micro.2007.23openalex-snapshot
Effective Optimistic-Checker Tandem Core Design through Architectural Pruning
inferred← citeshttps://doi.org/10.1109/micro.2007.39openalex-snapshot
Low-Cost Epoch-Based Correlation Prefetching for Commercial Applications
inferred← citeshttps://doi.org/10.1109/micro50266.2020.00054openalex-snapshot
Boosting Store Buffer Efficiency with Store-Prefetch Bursts
inferred← citeshttps://doi.org/10.1109/mm.2006.8openalex-snapshot
Coarse-Grain Coherence Tracking: RegionScout and Region Coherence Arrays
inferred← citeshttps://doi.org/10.1109/tc.2008.108openalex-snapshot
The Synonym Lookaside Buffer: A Solution to the Synonym Problem in Virtual Caches
inferred← citeshttps://doi.org/10.1145/1242531.1242536openalex-snapshot
An analysis of the effects of miss clustering on the cost of a cache miss
inferred← citeshttps://doi.org/10.1145/1250662.1250667openalex-snapshot
Making the fast case common and the uncommon case simple in unbounded transactional memory
inferred← citeshttps://doi.org/10.1145/1250662.1250684openalex-snapshot
Hardware atomicity for reliable software speculation
inferred← citeshttps://doi.org/10.1145/1250662.1250696openalex-snapshot
Mechanisms for store-wait-free multiprocessors
inferred← citeshttps://doi.org/10.1145/1273440.1250667openalex-snapshot
Making the fast case common and the uncommon case simple in unbounded transactional memory
inferred← citeshttps://doi.org/10.1145/1273440.1250684openalex-snapshot
Hardware atomicity for reliable software speculation
inferred← citeshttps://doi.org/10.1145/1273440.1250696openalex-snapshot
Mechanisms for store-wait-free multiprocessors
inferred← citeshttps://doi.org/10.1184/r1/6469421openalex-snapshot
The Main Memory System: Challenges and Opportunities
inferred← citeshttps://doi.org/10.13176/11.89openalex-snapshot
Processor Abstraction in Computer System Models
inferred← citeshttps://doi.org/10.14529/jsfi140302openalex-snapshot
Research Problems and Opportunities in Memory Systems
inferred← citeshttps://doi.org/10.31274/rtd-180813-16995openalex-snapshot
Performance analysis and optimization of the Java memory system
inferred← citeshttps://doi.org/10.48456/tr-697openalex-snapshot
Scaling Mount Concurrency: scalability and progress in concurrent algorithms
inferred← citeshttps://doi.org/10.48550/arxiv.1710.10746openalex-snapshot
Louvre: Lightweight Ordering Using Versioning for Release Consistency
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