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Coarse-Grain Coherence Tracking: RegionScout and Region Coherence Arrays

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1109/hpca.2001.903254openalex-snapshot
JETTY: filtering snoops for reduced energy consumption in SMP servers
inferredcites →https://doi.org/10.1109/isca.2005.31openalex-snapshot
Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking
inferredcites →https://doi.org/10.1109/isca.2005.42openalex-snapshot
RegionScout: Exploiting Coarse Grain Sharing in Snoop-Based Coherence
inferredcites →https://doi.org/10.1109/lpe.2002.146746openalex-snapshot
TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessors
inferredcites →https://doi.org/10.1109/micro.2005.31openalex-snapshot
Store Memory-Level Parallelism Optimizations for Commercial Applications
inferredcites →https://doi.org/10.1145/1080695.1069990openalex-snapshot
RegionScout
inferredcites →https://doi.org/10.1145/1080695.1069991openalex-snapshot
Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking
inferredcites →https://doi.org/10.1145/566408.566471openalex-snapshot
TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessors
inferredcites →https://doi.org/10.1145/582034.582041openalex-snapshot
The sun fireplane system interconnect

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-030-69131-8_14openalex-snapshot
Design of Reliable NoC Architectures
inferred← citeshttps://doi.org/10.1007/978-3-031-01764-3_10openalex-snapshot
Consistency and Coherence for Heterogeneous Systems
inferred← citeshttps://doi.org/10.1007/978-3-540-85451-7_16openalex-snapshot
To Snoop or Not to Snoop: Evaluation of Fine-Grain and Coarse-Grain Snoop Filtering Techniques
inferred← citeshttps://doi.org/10.1007/s10489-007-0095-6openalex-snapshot
PID control of MIMO process based on rank niching genetic algorithm
inferred← citeshttps://doi.org/10.1007/s11227-014-1288-5openalex-snapshot
PS-Cache: an energy-efficient cache design for chip multiprocessors
inferred← citeshttps://doi.org/10.1016/j.jpdc.2022.09.004openalex-snapshot
Fine-grain data classification to filter token coherence traffic
inferred← citeshttps://doi.org/10.1016/j.sysarc.2007.09.005openalex-snapshot
Using supplier locality in power-aware interconnects and caches in chip multiprocessors
inferred← citeshttps://doi.org/10.1109/ccece.2008.4564735openalex-snapshot
A simulation study of region-level coherence tracking in ring-based multiprocessors
inferred← citeshttps://doi.org/10.1109/date.2010.5457028openalex-snapshot
SigNet: Network-on-chip filtering for coarse vector directories
inferred← citeshttps://doi.org/10.1109/dsd.2010.85openalex-snapshot
Filtering Directory Lookups in CMPs
inferred← citeshttps://doi.org/10.1109/hpca.2008.4658649openalex-snapshot
Power-Efficient DRAM Speculation
inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00078openalex-snapshot
Delegated Replies: Alleviating Network Clogging in Heterogeneous Architectures
inferred← citeshttps://doi.org/10.1109/icece.2010.212openalex-snapshot
Development of the Temperature Sensor for Measuring Heat Based on the Difference between the Specific Enthalpy
inferred← citeshttps://doi.org/10.1109/icpads.2009.32openalex-snapshot
Snooping and Ordering Ring - An Efficient Cache Coherence Protocol for Ring Connected CMP
inferred← citeshttps://doi.org/10.1109/icpp.2013.70openalex-snapshot
Temporal-Aware Mechanism to Detect Private Data in Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/ipdps.2007.370533openalex-snapshot
A Power-Aware Prediction-Based Cache Coherence Protocol for Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/isca.2018.00031openalex-snapshot
Spandex: A Flexible Interface for Efficient Heterogeneous Coherence
inferred← citeshttps://doi.org/10.1109/micro.2016.7783739openalex-snapshot
C3D: Mitigating the NUMA bottleneck via coherent DRAM caches
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00058openalex-snapshot
CPElide: Efficient Multi-Chiplet GPU Implicit Synchronization
inferred← citeshttps://doi.org/10.1109/tpds.2010.43openalex-snapshot
A Direct Coherence Protocol for Many-Core Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/tpds.2013.26openalex-snapshot
Extending the Performance and Energy-Efficiency of Shared Memory Multicores with Nanophotonic Technology
inferred← citeshttps://doi.org/10.1109/tpds.2015.2412139openalex-snapshot
Efficient TLB-Based Detection of Private Pages in Chip Multiprocessors
inferred← citeshttps://doi.org/10.1145/1168857.1168892openalex-snapshot
Stealth prefetching
inferred← citeshttps://doi.org/10.1145/1242531.1242568openalex-snapshot
Speculative supplier identification for reducing power of interconnects in snoopy cache coherence protocols
inferred← citeshttps://doi.org/10.1145/1393921.1393988openalex-snapshot
Energy-efficient MESI cache coherence with pro-active snoop filtering for multicore microprocessors
inferred← citeshttps://doi.org/10.1145/1854273.1854291openalex-snapshot
WAYPOINT
inferred← citeshttps://doi.org/10.1145/2541228.2555307openalex-snapshot
WADE
inferred← citeshttps://doi.org/10.1145/2555289.2555307openalex-snapshot
WADE
inferred← citeshttps://doi.org/10.1145/2925426.2926280openalex-snapshot
TokenTLB
inferred← citeshttps://doi.org/10.1145/3530819openalex-snapshot
A Case for Fine-grain Coherence Specialization in Heterogeneous Systems
inferred← citeshttps://doi.org/10.2200/s00962ed2v01y201910cac049openalex-snapshot
A Primer on Memory Consistency and Cache Coherence, Second Edition
inferred← citeshttps://doi.org/10.26076/027f-6b3eopenalex-snapshot
Design of Reliable and Secure Network-On-Chip Architectures
inferred← citeshttps://doi.org/10.4995/thesis/10251/79551openalex-snapshot
Improving Energy and Area Scalability of the Cache Hierarchy in CMPs
inferred← citeshttps://doi.org/10.4995/thesis/10251/86136openalex-snapshot
Design of Efficient TLB-based Data Classification Mechanisms in Chip Multiprocessors
inferred← citeshttps://doi.org/10.4995/thesis/10251/86187openalex-snapshot
Design of Efficient TLB-based Data Classification Mechanisms in Chip Multiprocessors
inferred← citeshttps://doi.org/10.5555/1870926.1871260openalex-snapshot
SigNet: network-on-chip filtering for coarse vector directories
inferred← citeshttps://doi.org/10.5555/2485288.2485536openalex-snapshot
Proactive aging management in heterogeneous NoCs through a criticality-driven routing approach
inferred← citeshttps://doi.org/10.5555/2523721.2523778openalex-snapshot
PS-cache: an energy-efficient cache design for chip multiprocessors
inferred← citeshttps://doi.org/10.5555/3195638.3195681openalex-snapshot
C 3 D: Mitigating the NUMA bottleneck via coherent DRAM caches
inferred← citeshttps://doi.org/10.5772/9454openalex-snapshot
Cache Coherence Protocols for Many-Core CMPs
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