On the public citation graph

The Cell Processor Architecture

https://doi.org/10.1109/micro.2005.33
0 signed · 48 inferred · view as graph

Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.

Is this your work? Sign in with ORCID and put your name on the claims that are yours.
Claim with ORCID
Reference health. See whether every reference in this work resolves to a known work and none has been retracted — and get a dated CiteStamped badge you can embed.
See reference health

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

inferred← citeshttps://doi.org/10.1007/978-3-030-27562-4_10openalex-snapshot
Platform-Agnostic Learning-Based Scheduling
inferred← citeshttps://doi.org/10.1007/978-3-540-85451-7_78openalex-snapshot
Meta-programming Applied to Automatic SMP Parallelization of Linear Algebra Code
inferred← citeshttps://doi.org/10.1007/978-3-642-03869-3_15openalex-snapshot
Hybrid Techniques for Fast Multicore Simulation
inferred← citeshttps://doi.org/10.1016/j.jss.2014.06.058openalex-snapshot
Hybrid address spaces: A methodology for implementing scalable high-level programming models on non-coherent many-core architectures
inferred← citeshttps://doi.org/10.1093/comjnl/bxq026openalex-snapshot
Local Memory Design Space Exploration for High-Performance Computing
inferred← citeshttps://doi.org/10.1109/aeect.2013.6716444openalex-snapshot
Gpu-based personal supercomputing
inferred← citeshttps://doi.org/10.1109/ahs.2010.5546268openalex-snapshot
An emerging adaptive architecture and compilation techniques
inferred← citeshttps://doi.org/10.1109/asicon.2009.5351277openalex-snapshot
Implementation and evaluation of a heterogeneous multicore SoC
inferred← citeshttps://doi.org/10.1109/bicta.2010.5645120openalex-snapshot
Porting Molecular Dynamics simulation to heterogeneous multi-core architecture
inferred← citeshttps://doi.org/10.1109/cadcg.2007.4407942openalex-snapshot
Comparison and Analysis of Novel Architectures for Media Compression
inferred← citeshttps://doi.org/10.1109/chinagrid.2010.41openalex-snapshot
A Multi-node MPI Implementation on the CellBE Processor
inferred← citeshttps://doi.org/10.1109/cit.2010.492openalex-snapshot
cCell: A S2S Compiler with Profiling Support for the Cell BE Architecture
inferred← citeshttps://doi.org/10.1109/hpcc.2008.134openalex-snapshot
A Profile-based Memory Access Optimizing Technology on CBE Architecture
inferred← citeshttps://doi.org/10.1109/ipdps.2008.4536314openalex-snapshot
Evaluating the role of scratchpad memories in chip multiprocessors for sparse matrix computations
inferred← citeshttps://doi.org/10.1109/ipdpsw.2010.5470910openalex-snapshot
T-NUCA - a novel approach to non-uniform access latency cache architectures for 3D CMPs
inferred← citeshttps://doi.org/10.1109/jssc.2022.3140241openalex-snapshot
Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory
inferred← citeshttps://doi.org/10.1109/mcsoc64144.2024.00038openalex-snapshot
Two-level Routerless Network-on-Chip
inferred← citeshttps://doi.org/10.1109/micro.2006.25openalex-snapshot
Fairness and Throughput in Switch on Event Multithreading
inferred← citeshttps://doi.org/10.1109/micro.2010.36openalex-snapshot
Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?
inferred← citeshttps://doi.org/10.1109/nas.2013.10openalex-snapshot
A HW/SW Co-design of Execution Migration for Shared-ISA Heterogeneous Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/nssmic.2009.5402412openalex-snapshot
PET 3D iterative reconstruction on Cell BE
inferred← citeshttps://doi.org/10.1109/pact.2015.26openalex-snapshot
Runtime-Guided Management of Scratchpad Memories in Multicore Architectures
inferred← citeshttps://doi.org/10.1109/sbac-pad.2008.19openalex-snapshot
Measuring Operating System Overhead on CMT Processors
inferred← citeshttps://doi.org/10.1109/sc.2012.61openalex-snapshot
Hardware-software coherence protocol for the coexistence of caches and local memories
inferred← citeshttps://doi.org/10.1109/tc.2013.194openalex-snapshot
Hardware–Software Coherence Protocol for the Coexistence of Caches and Local Memories
inferred← citeshttps://doi.org/10.1145/1275937.1275939openalex-snapshot
Fairness enforcement in switch on event multithreading
inferred← citeshttps://doi.org/10.1145/1328195.1328201openalex-snapshot
Hiding the misprediction penalty of a resource-efficient high-performance processor
inferred← citeshttps://doi.org/10.1145/1735970.1736044openalex-snapshot
Conservation cores
inferred← citeshttps://doi.org/10.1145/1735971.1736044openalex-snapshot
Conservation cores
inferred← citeshttps://doi.org/10.1145/1736020.1736044openalex-snapshot
Conservation cores
inferred← citeshttps://doi.org/10.1145/1950413.1950435openalex-snapshot
CoRAM
inferred← citeshttps://doi.org/10.1145/2749469.2750411openalex-snapshot
Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures
inferred← citeshttps://doi.org/10.1145/2872887.2750411openalex-snapshot
Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures
inferred← citeshttps://doi.org/10.1145/2989081.2989087openalex-snapshot
Data-Centric Computing Frontiers
inferred← citeshttps://doi.org/10.1145/3303084.3309492openalex-snapshot
Deciphering Predictive Schedulers for Heterogeneous-ISA Multicore Architectures
inferred← citeshttps://doi.org/10.1147/jrd.2018.2846978openalex-snapshot
Functionality and performance of NVLink with IBM POWER9 processors
inferred← citeshttps://doi.org/10.1360/n112016-00147openalex-snapshot
Emerging High-Performance Computing Systems and Technology
inferred← citeshttps://doi.org/10.25560/17837openalex-snapshot
Communication Optimization in Iterative Numerical Algorithms: An Algorithm-Architecture Interaction
inferred← citeshttps://doi.org/10.4018/978-1-4666-0906-8.ch008openalex-snapshot
On the Path to Exascale
inferred← citeshttps://doi.org/10.4018/978-1-4666-9466-8.ch105openalex-snapshot
GPU Scaling
inferred← citeshttps://doi.org/10.4018/ijitwe.2014100102openalex-snapshot
GPU Scaling
inferred← citeshttps://doi.org/10.4018/jdst.2010040101openalex-snapshot
On the Path to Exascale
inferred← citeshttps://doi.org/10.48550/arxiv.2109.00665openalex-snapshot
Agon: A Scalable Competitive Scheduler for Large Heterogeneous Systems
inferred← citeshttps://doi.org/10.53846/goediss-3291openalex-snapshot
NEW COMPUTATIONAL METHODS FOR 3D STRUCTURE DETERMINATION OF MACROMOLECULAR COMPLEXES BY SINGLE PARTICLE CRYO-ELECTRON MICROSCOPY
inferred← citeshttps://doi.org/10.5445/ir/1000027114openalex-snapshot
Parallel Preconditioners for an Ocean Model in Climate Simulations
inferred← citeshttps://doi.org/10.5555/2388996.2389117openalex-snapshot
Hardware-software coherence protocol for the coexistence of caches and local memories
inferred← citeshttps://doi.org/10.5821/dissertation-2117-125507openalex-snapshot
Hardware runtime management for task-based programming models
inferred← citeshttps://doi.org/10.5821/dissertation-2117-96004openalex-snapshot
Transparent management of scratchpad memories in shared memory programming models
Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.