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Authentication Control Point and Its Implications For Secure Processor Design
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/11587514_11openalex-snapshot
Memory-Centric Security Architecture
inferredcites →https://doi.org/10.1007/3-540-44709-1_7openalex-snapshot
High Performance Single-Chip FPGA Rijndael Algorithm Implementations
inferredcites →https://doi.org/10.1007/978-3-540-71528-3_7openalex-snapshot
Memory-Centric Security Architecture
inferredcites →https://doi.org/10.1007/s00145-004-0016-3openalex-snapshot
CBC MACs for Arbitrary-Length Messages: The Three-Key Constructions
inferredcites →https://doi.org/10.1016/j.jpdc.2006.04.011openalex-snapshot
M-TREE: A high efficiency security architecture for protecting integrity and privacy of software
inferredcites →https://doi.org/10.1109/acssc.2003.1292360openalex-snapshot
Speed-area trade-off for 10 to 100 Gbits/s throughput AES processor
inferredcites →https://doi.org/10.1109/cgo.2003.1191556openalex-snapshot
Hiding program slices for software security
inferredcites →https://doi.org/10.1109/isvlsi.2004.1339512openalex-snapshot
Minimum area cost for a 30 to 70 Gbits/s AES processor
inferredcites →https://doi.org/10.1109/micro.2003.1253207openalex-snapshot
Efficient memory integrity verification and encryption for secure processors
inferredcites →https://doi.org/10.1109/micro.2003.1253209openalex-snapshot
Fast secure processor for inhibiting software piracy and tampering
inferredcites →https://doi.org/10.1109/micro.2004.31openalex-snapshot
RIFLE: An Architectural Framework for User-Centric Information-Flow Security
inferredcites →https://doi.org/10.1145/1023833.1023873openalex-snapshot
Hardware assisted control flow obfuscation for embedded processors
inferredcites →https://doi.org/10.1145/1055626.1055629openalex-snapshot
Towards the issues in architectural support for protection of software execution
inferredcites →https://doi.org/10.1145/1080695.1069972openalex-snapshot
High Efficiency Counter Mode Security Architecture via Prediction and Precomputation
inferredcites →https://doi.org/10.1145/1150019.1136502openalex-snapshot
Improving Cost, Performance, and Security of Memory Encryption and Authentication
inferredcites →https://doi.org/10.1145/1152154.1152169openalex-snapshot
A low-cost memory remapping scheme for address bus protection
inferredcites →https://doi.org/10.1145/233551.233553openalex-snapshot
Software protection and simulation on oblivious RAMs
inferredcites →https://doi.org/10.1145/356989.357005openalex-snapshot
Architectural support for copy and tamper resistant software
inferredcites →https://doi.org/10.1145/378995.379237openalex-snapshot
Architectural support for copy and tamper resistant software
inferredcites →https://doi.org/10.1145/581888.581894openalex-snapshot
Frequent value locality and its applications
inferredcites →https://doi.org/10.1145/605397.605403openalex-snapshot
Automatically characterizing large scale program behavior
inferredcites →https://doi.org/10.1201/9781439821916openalex-snapshot
Handbook of Applied Cryptography
inferredcites →https://doi.org/10.17487/rfc2104openalex-snapshot
HMAC: Keyed-Hashing for Message Authentication
inferredcites →https://doi.org/10.3929/ethz-a-004287049openalex-snapshot
Performance evaluation of recent DRAM architectures for embedded systems
inferredcites →https://doi.org/10.5555/1025127.1026002openalex-snapshot
Architectural Support for High Speed Protection of Memory Integrity and Confidentiality in Multiprocessor Systems
inferredcites →https://doi.org/10.5555/776261.776297openalex-snapshot
Hiding program slices for software security
inferredcites →https://doi.org/10.5555/956417.956575openalex-snapshot
Efficient memory integrity verification and encryption for secure processors
inferredcites →https://doi.org/10.5860/choice.34-4512openalex-snapshot
Handbook of applied cryptography
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-642-17499-5_13openalex-snapshot
Green Secure Processors: Towards Power-Efficient Secure Processor Design
inferred← citeshttps://doi.org/10.1016/j.sysarc.2025.103568openalex-snapshot
SecScale : A Scalable and Secure Trusted Execution Environment for Servers
inferred← citeshttps://doi.org/10.1016/j.sysarc.2026.103974openalex-snapshot
Memory Access Control Extension (MACE): An efficient solution for securing chiplet-systems
inferred← citeshttps://doi.org/10.1109/access.2023.3275757openalex-snapshot
Microarchitectural Side-Channel Threats, Weaknesses and Mitigations: A Systematic Mapping Study
inferred← citeshttps://doi.org/10.1109/csf.2013.11openalex-snapshot
Memory Trace Oblivious Program Execution
inferred← citeshttps://doi.org/10.1109/dcabes.2014.57openalex-snapshot
Memory Integrity Protection Method Based on Asymmetric Hash Tree
inferred← citeshttps://doi.org/10.1109/hpca.2008.4658636openalex-snapshot
Single-level integrity and confidentiality protection for distributed shared memory multiprocessors
inferred← citeshttps://doi.org/10.1109/hpca.2013.6522323openalex-snapshot
Architecture support for guest-transparent VM protection from untrusted hypervisor and physical attacks
inferred← citeshttps://doi.org/10.1109/hpca.2018.00045openalex-snapshot
Comprehensive VM Protection Against Untrusted Hypervisor Through Retrofitted AMD Memory Encryption
inferred← citeshttps://doi.org/10.1109/hpca.2018.00046openalex-snapshot
SYNERGY: Rethinking Secure-Memory Design for Error-Correcting Memories
inferred← citeshttps://doi.org/10.1109/isvlsi.2019.00066openalex-snapshot
FAST: A Frequency-Aware Skewed Merkle Tree for FPGA-Secured Embedded Systems
inferred← citeshttps://doi.org/10.1109/micro.2007.16openalex-snapshot
Using Address Independent Seed Encryption and Bonsai Merkle Trees to Make Secure Processors OS- and Performance-Friendly
inferred← citeshttps://doi.org/10.1109/micro.2014.39openalex-snapshot
A Practical Methodology for Measuring the Side-Channel Signal Available to the Attacker for Instruction-Level Events
inferred← citeshttps://doi.org/10.1109/micro.2016.7783741openalex-snapshot
PoisonIvy: Safe speculation for secure memory
inferred← citeshttps://doi.org/10.1109/micro.2018.00041openalex-snapshot
Morphable Counters: Enabling Compact Integrity Trees For Low-Overhead Secure Memories
inferred← citeshttps://doi.org/10.1109/sp46215.2023.10179390openalex-snapshot
CSI:Rowhammer – Cryptographic Security and Integrity against Rowhammer
inferred← citeshttps://doi.org/10.1109/tcad.2019.2948914openalex-snapshot
Fork Path: Batching ORAM Requests to Remove Redundant Memory Accesses
inferred← citeshttps://doi.org/10.1109/tcad.2024.3448264openalex-snapshot
PreSIT: Predict Cryptography Computations in SGX-Style Integrity Trees
inferred← citeshttps://doi.org/10.1109/tcc.2015.2511728openalex-snapshot
Architectural Protection of Application Privacy against Software and Physical Attacks in Untrusted Cloud Environment
inferred← citeshttps://doi.org/10.1109/tdsc.2025.3630054openalex-snapshot
Coeus: Secure Similarity-Aware Data Integrity Verification for Secure Memories
inferred← citeshttps://doi.org/10.1145/1242531.1242539openalex-snapshot
Accelerating memory decryption and authentication with frequent value prediction
inferred← citeshttps://doi.org/10.1145/1498690.1498691openalex-snapshot
Making secure processors OS- and performance-friendly
inferred← citeshttps://doi.org/10.1145/2482767.2482799openalex-snapshot
Multi-processor architectural support for protecting virtual machine privacy in untrusted cloud environment
inferred← citeshttps://doi.org/10.1145/3620666.3651354openalex-snapshot
A Midsummer Night’s Tree: Efficient and High Performance Secure SCM
inferred← citeshttps://doi.org/10.1145/3622781.3674168openalex-snapshot
TensorTEE: Unifying Heterogeneous TEE Granularity for Efficient Secure Collaborative Tensor Computing
inferred← citeshttps://doi.org/10.1145/3622781.3674180openalex-snapshot
Toleo: Scaling Freshness to Tera-scale Memory Using CXL and PIM
inferred← citeshttps://doi.org/10.4018/ijmstr.2015040105openalex-snapshot
Design and Performance Evaluation of the SCAN Secure Processor
inferred← citeshttps://doi.org/10.5555/3195638.3195684openalex-snapshot
Poisonivy: safe speculation for secure memory
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