On the public citation graph
AEGIS
0 signed · 314 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1016/s1389-1286(98)00019-xopenalex-snapshot
Building a high-performance, programmable secure coprocessor
inferredcites →https://doi.org/10.1109/2.869367openalex-snapshot
SPEC CPU2000: measuring CPU performance in the New Millennium
inferredcites →https://doi.org/10.1109/sp.1980openalex-snapshot
1980 IEEE Symposium on Security and Privacy
inferredcites →https://doi.org/10.1109/tit.1976.1055638openalex-snapshot
New directions in cryptography
inferredcites →https://doi.org/10.1145/233551.233553openalex-snapshot
Software protection and simulation on oblivious RAMs
inferredcites →https://doi.org/10.1145/359340.359342openalex-snapshot
A method for obtaining digital signatures and public-key cryptosystems
inferredcites →https://doi.org/10.1145/378993.379237openalex-snapshot
Architectural support for copy and tamper resistant software
inferredcites →https://doi.org/10.1145/513918.514079openalex-snapshot
Unlocking the design secrets of a 2.29 Gb/s Rijndael processor
inferredcites →https://doi.org/10.1145/586110.586132openalex-snapshot
Silicon physical random functions
inferredcites →https://doi.org/10.1145/643477.643479openalex-snapshot
(How) can mobile agents do secure electronic transactions on untrusted hosts? A survey of the security issues and the current solutions
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/9781118557624.ch5openalex-snapshot
Hardware Security in Embedded Systems
inferred← citeshttps://doi.org/10.1002/tee.22123openalex-snapshot
An XOR‐based parameterization for instruction register files
inferred← citeshttps://doi.org/10.1007/1-4020-8090-5_5openalex-snapshot
Trusted Computing, Peer-to-Peer Distribution, and The Economics of Pirated Entertainment
inferred← citeshttps://doi.org/10.1007/11572961_52openalex-snapshot
Efficient Architectural Support for Secure Bus-Based Shared Memory Multiprocessor
inferred← citeshttps://doi.org/10.1007/11587514_11openalex-snapshot
Memory-Centric Security Architecture
inferred← citeshttps://doi.org/10.1007/11601494_3openalex-snapshot
Remote Software-Based Attestation for Wireless Sensors
inferred← citeshttps://doi.org/10.1007/11682127_31openalex-snapshot
A Cache Design for a Security Architecture for Microprocessors (SAM)
inferred← citeshttps://doi.org/10.1007/11839569_22openalex-snapshot
Daonity: An Experience on Enhancing Grid Security by Trusted Computing Technology
inferred← citeshttps://doi.org/10.1007/11847083_26openalex-snapshot
A Comparison of Two Approaches Providing Data Encryption and Authentication on a Processor Memory Bus
inferred← citeshttps://doi.org/10.1007/978-0-387-77322-3_7openalex-snapshot
Towards a Virtualization-enabled Framework for Information Traceability (VFIT)
inferred← citeshttps://doi.org/10.1007/978-3-031-21377-9_6openalex-snapshot
Toward Fully Functional Encrypted Databases
inferred← citeshttps://doi.org/10.1007/978-3-319-13257-0_16openalex-snapshot
SystemWall: An Isolated Firewall Using Hardware-Based Memory Introspection
inferred← citeshttps://doi.org/10.1007/978-3-319-14971-4_1openalex-snapshot
Disorder-Based Security Hardware: An Overview
inferred← citeshttps://doi.org/10.1007/978-3-319-17533-1_2openalex-snapshot
Expanding an Operating System’s Working Space with a New Mode to Support Trust Measurement
inferred← citeshttps://doi.org/10.1007/978-3-319-18467-8_37openalex-snapshot
The Dual-Execution-Environment Approach: Analysis and Comparative Evaluation
inferred← citeshttps://doi.org/10.1007/978-3-319-24644-4_6openalex-snapshot
A Theory of Integrating Tamper Evidence with Stabilization
inferred← citeshttps://doi.org/10.1007/978-3-319-56620-7_10openalex-snapshot
Formal Abstractions for Attested Execution Secure Processors
inferred← citeshttps://doi.org/10.1007/978-3-319-99136-8_2openalex-snapshot
Secure Code Execution: A Generic PUF-Driven System Architecture
inferred← citeshttps://doi.org/10.1007/978-3-540-25980-0_18openalex-snapshot
Distributing Security-Mediated PKI
inferred← citeshttps://doi.org/10.1007/978-3-540-71528-3_7openalex-snapshot
Memory-Centric Security Architecture
inferred← citeshttps://doi.org/10.1007/978-3-540-72590-9_83openalex-snapshot
Encoding-Based Tamper-Resistant Algorithm for Mobile Device Security
inferred← citeshttps://doi.org/10.1007/978-3-540-74810-6_10openalex-snapshot
Trusted Mobile Platforms
inferred← citeshttps://doi.org/10.1007/978-3-540-79104-1_11openalex-snapshot
Secure Cryptographic Precomputation with Insecure Memory
inferred← citeshttps://doi.org/10.1007/978-3-540-79104-1_12openalex-snapshot
Securing Peer-to-Peer Distributions for Mobile Devices
inferred← citeshttps://doi.org/10.1007/978-3-540-85893-5_10openalex-snapshot
The Trusted Execution Module: Commodity General-Purpose Trusted Computing
inferred← citeshttps://doi.org/10.1007/978-3-642-00955-6_26openalex-snapshot
Building Secure Resources to Ensure Safe Computations in Distributed and Potentially Corrupted Environments
inferred← citeshttps://doi.org/10.1007/978-3-642-14597-1_1openalex-snapshot
On Design of a Trusted Software Base with Support of TPCM
inferred← citeshttps://doi.org/10.1007/978-3-642-22339-6_10openalex-snapshot
Using Counter Cache Coherence to Improve Memory Encryptions Performance in Multiprocessor Systems
inferred← citeshttps://doi.org/10.1007/978-3-642-31540-4_23openalex-snapshot
Improving Virtualization Security by Splitting Hypervisor into Smaller Components
inferred← citeshttps://doi.org/10.1007/978-3-662-46494-6_18openalex-snapshot
Locally Decodable and Updatable Non-malleable Codes and Their Applications
inferred← citeshttps://doi.org/10.1007/978-3-662-48797-6_15openalex-snapshot
Oblivious Network RAM and Leveraging Parallelism to Achieve Obliviousness
inferred← citeshttps://doi.org/10.1007/978-3-662-53357-4_20openalex-snapshot
Using Intel Software Guard Extensions for Efficient Two-Party Secure Function Evaluation
inferred← citeshttps://doi.org/10.1007/978-94-007-1338-3_6openalex-snapshot
Embedded Systems Security for FPGA
inferred← citeshttps://doi.org/10.1007/978-94-007-2105-0_24openalex-snapshot
VIsolator: An Intel VMX-Based Isolation Mechanism
inferred← citeshttps://doi.org/10.1007/s10207-004-0033-0openalex-snapshot
Outbound authentication for programmable secure coprocessors
inferred← citeshttps://doi.org/10.1007/s10207-005-0076-xopenalex-snapshot
Distributing security-mediated PKI
inferred← citeshttps://doi.org/10.1007/s10836-013-5430-8openalex-snapshot
Counterfeit Integrated Circuits: Detection, Avoidance, and the Challenges Ahead
inferred← citeshttps://doi.org/10.1007/s10922-012-9253-1openalex-snapshot
Security-Preserving Live Migration of Virtual Machines in the Cloud
inferred← citeshttps://doi.org/10.1007/s11227-010-0465-4openalex-snapshot
Efficient scheme of verifying integrity of application binaries in embedded operating systems
inferred← citeshttps://doi.org/10.1007/s11416-007-0062-0openalex-snapshot
Improving virus protection with an efficient secure architecture with memory encryption, integrity and information leakage protection
inferred← citeshttps://doi.org/10.1007/s13389-018-0180-2openalex-snapshot
MEAS: memory encryption and authentication secure against side-channel attacks
inferred← citeshttps://doi.org/10.1007/s41635-020-00108-8openalex-snapshot
Towards Designing a Secure RISC-V System-on-Chip: ITUS
inferred← citeshttps://doi.org/10.1016/b978-0-12-373892-9.00010-4openalex-snapshot
Verification and Security Issues in On-Chip Communication Architecture Design
inferred← citeshttps://doi.org/10.1016/b978-0-12-415815-3.00012-1openalex-snapshot
Hardware and Security
inferred← citeshttps://doi.org/10.1016/j.cose.2009.03.002openalex-snapshot
Providing secure execution environments with a last line of defense against Trojan circuit attacks
inferred← citeshttps://doi.org/10.1016/j.istr.2007.05.005openalex-snapshot
Daonity – Grid security from two levels of virtualization
inferred← citeshttps://doi.org/10.1016/j.jpdc.2009.11.008openalex-snapshot
A low-cost memory remapping scheme for address bus protection
inferred← citeshttps://doi.org/10.1080/01611190802231140openalex-snapshot
Trusted Computing: Security and Applications
inferred← citeshttps://doi.org/10.1109/access.2018.2881447openalex-snapshot
A Security Design for the Detecting of Buffer Overflow Attacks in IoT Device
inferred← citeshttps://doi.org/10.1109/acsac.2006.21openalex-snapshot
CryptoPage: An Efficient Secure Architecture with Memory Encryption, Integrity and Information Leakage Protection
inferred← citeshttps://doi.org/10.1109/acsac.2009.19openalex-snapshot
Scalable Web Content Attestation
inferred← citeshttps://doi.org/10.1109/apccas62602.2024.10808709openalex-snapshot
A Lightweight Memory Protection Scheme with Criticality-Aware Encryption and Embedded MAC for Secure DNN Accelerators
inferred← citeshttps://doi.org/10.1109/asianhost.2017.8354005openalex-snapshot
Obfuscating branch decisions based on encrypted data using MISR and hash digests
inferred← citeshttps://doi.org/10.1109/aspdac.2016.7428088openalex-snapshot
SPARTA: A scheduling policy for thwarting differential power analysis attacks
inferred← citeshttps://doi.org/10.1109/candar.2016.0068openalex-snapshot
Last Path Caching: A Simple Way to Remove Redundant Memory Accesses of Path ORAM
inferred← citeshttps://doi.org/10.1109/ccgrid59990.2024.00015openalex-snapshot
PireSPM: Efficient and Recoverable Secure Persistent Memory for Multi-cores
inferred← citeshttps://doi.org/10.1109/codesisss.2015.7331377openalex-snapshot
Computer security by hardware-intrinsic authentication
inferred← citeshttps://doi.org/10.1109/compsac57700.2023.00144openalex-snapshot
Deep Learning based Security Enhancement of Wireless Connectivity
inferred← citeshttps://doi.org/10.1109/csae.2011.5953301openalex-snapshot
Customized program protection for a user customized data protection framework
inferred← citeshttps://doi.org/10.1109/csitss.2018.8768739openalex-snapshot
Multivariate Solutions for Digital Rights Management Using Hardware and Software Methods-Survey
inferred← citeshttps://doi.org/10.1109/dac.2006.229264openalex-snapshot
A parallelized way to provide data encryption and integrity checking on a processor-memory bus
inferred← citeshttps://doi.org/10.1109/dac.2018.8465847openalex-snapshot
Reducing the Overhead of Authenticated Memory Encryption Using Delta Encoding and ECC Memory
inferred← citeshttps://doi.org/10.1109/dac.2018.8465863openalex-snapshot
Hypernel: A Hardware-Assisted Framework for Kernel Protection without Nested Paging
inferred← citeshttps://doi.org/10.1109/dasc-picom-datacom-cyberscitec.2017.100openalex-snapshot
Systematic Test Generation for Secure Hardware Supported Virtualization
inferred← citeshttps://doi.org/10.1109/dasc.2009.5347415openalex-snapshot
Compiler/hardware assisted application code and data security in embedded systems
inferred← citeshttps://doi.org/10.1109/dcabes.2012.55openalex-snapshot
Memory Confidentiality and Integrity Protection Method Based on Variable Length Counter
inferred← citeshttps://doi.org/10.1109/desec.2017.8073840openalex-snapshot
Computing with obfuscated data in arbitrary logic circuits via noise insertion and cancellation
inferred← citeshttps://doi.org/10.1109/dsn53405.2022.00053openalex-snapshot
ERIC: An Efficient and Practical Software Obfuscation Framework
inferred← citeshttps://doi.org/10.1109/dsnw.2011.5958816openalex-snapshot
Secure MMU: Architectural support for memory isolation among virtual machines
inferred← citeshttps://doi.org/10.1109/ets.2015.7138763openalex-snapshot
Cyber-physical systems: A security perspective
inferred← citeshttps://doi.org/10.1109/eurosp.2016.24openalex-snapshot
Fine-Grained Control-Flow Integrity for Kernel Software
inferred← citeshttps://doi.org/10.1109/globalsip.2016.7905989openalex-snapshot
Reliable secret-key binding for physical unclonable functions with transform coding
inferred← citeshttps://doi.org/10.1109/hpca.2005.31openalex-snapshot
SENSS: Security Enhancement to Symmetric Shared Memory Multiprocessors
inferred← citeshttps://doi.org/10.1109/hpca.2013.6522323openalex-snapshot
Architecture support for guest-transparent VM protection from untrusted hypervisor and physical attacks
inferred← citeshttps://doi.org/10.1109/hpca.2017.36openalex-snapshot
Camouflage: Memory Traffic Shaping to Mitigate Timing Attacks
inferred← citeshttps://doi.org/10.1109/hpca.2018.00043openalex-snapshot
D-ORAM: Path-ORAM Delegation for Low Execution Interference on Cloud Servers with Untrusted Memory
inferred← citeshttps://doi.org/10.1109/hpca.2018.00045openalex-snapshot
Comprehensive VM Protection Against Untrusted Hypervisor Through Retrofitted AMD Memory Encryption
inferred← citeshttps://doi.org/10.1109/hpca47549.2020.00019openalex-snapshot
IRONHIDE: A Secure Multicore that Efficiently Mitigates Microarchitecture State Attacks for Interactive Applications
inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00011openalex-snapshot
Common Counters: Compressed Encryption Counters for Secure GPU Memory
inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00034openalex-snapshot
IR-ORAM: Path Access Type Based Memory Intensity Reduction for Path-ORAM
inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10071064openalex-snapshot
AB-ORAM: Constructing Adjustable Buckets for Space Reduction in Ring ORAM
inferred← citeshttps://doi.org/10.1109/hpca57654.2024.00026openalex-snapshot
Data Enclave: A Data-Centric Trusted Execution Environment
inferred← citeshttps://doi.org/10.1109/hst.2009.5225055openalex-snapshot
Temperature-aware cooperative ring oscillator PUF
inferred← citeshttps://doi.org/10.1109/hst.2010.5513105openalex-snapshot
LISA: Maximizing RO PUF's secret extraction
inferred← citeshttps://doi.org/10.1109/hst.2016.7495567openalex-snapshot
SDSM: Fast and scalable security support for directory-based distributed shared memory
inferred← citeshttps://doi.org/10.1109/hst.2016.7495578openalex-snapshot
A key-centric processor architecture for secure computing
inferred← citeshttps://doi.org/10.1109/hst.2017.7951732openalex-snapshot
Reviving instruction set randomization
inferred← citeshttps://doi.org/10.1109/iaw.2007.381946openalex-snapshot
Memoization Attacks and Copy Protection in Partitioned Applications
inferred← citeshttps://doi.org/10.1109/icc.2017.7996732openalex-snapshot
Secret-key binding to physical identifiers with reliability guarantees
inferred← citeshttps://doi.org/10.1109/iccad.2017.8203804openalex-snapshot
Hardening extended memory access control schemes with self-verified address spaces
inferred← citeshttps://doi.org/10.1109/iccd.2007.4601899openalex-snapshot
Compiler-assisted architectural support for program code integrity monitoring in application-specific instruction set processors
inferred← citeshttps://doi.org/10.1109/iccd.2009.5413140openalex-snapshot
SHIELDSTRAP: Making secure processors truly secure
inferred← citeshttps://doi.org/10.1109/iccd.2018.00026openalex-snapshot
Breaking the Oblivious-RAM Bandwidth Wall
inferred← citeshttps://doi.org/10.1109/iccea.2010.109openalex-snapshot
Hardware Assisted Address Monitoring System
inferred← citeshttps://doi.org/10.1109/icdcs.2005.85openalex-snapshot
Virtual Leashing: Internet-Based Software Piracy Protection
inferred← citeshttps://doi.org/10.1109/icdcsw.2011.51openalex-snapshot
A Case for Hardware Protection of Guest VMs from Compromised Hypervisors in Cloud Computing
inferred← citeshttps://doi.org/10.1109/icess.2008.59openalex-snapshot
Design and Implementation of Secure Embedded Systems Based on Trustzone
inferred← citeshttps://doi.org/10.1109/icitis.2010.5688775openalex-snapshot
Architectural-enhanced intrusion detection and memory authentication schemes in embedded systems
inferred← citeshttps://doi.org/10.1109/icsai.2012.6223593openalex-snapshot
MGT: A multi-grained memory hash mechanism for embedded processor
inferred← citeshttps://doi.org/10.1109/icsamos.2007.4285752openalex-snapshot
Secure and Authenticated Communication in Chip-Level Microcomputer Bus Systems with Tree Parity Machines
inferred← citeshttps://doi.org/10.1109/icsess.2017.8342994openalex-snapshot
A novel security validation in embedded system
inferred← citeshttps://doi.org/10.1109/icsess.2018.8663802openalex-snapshot
An Architectural-Enhanced Secure Design in Embedded System
inferred← citeshttps://doi.org/10.1109/icut.2010.5677650openalex-snapshot
Visualization of Trusted Multi-Clients Monitoring with TPM
inferred← citeshttps://doi.org/10.1109/icvd.2004.1260985openalex-snapshot
Tamper resistance mechanisms for secure embedded systems
inferred← citeshttps://doi.org/10.1109/icwus.2010.5670446openalex-snapshot
Enforcing the security of component-based embedded systems with Information Flow Control
inferred← citeshttps://doi.org/10.1109/indin.2015.7281938openalex-snapshot
Blind hypervision to protect virtual machine privacy against hypervisor escape vulnerabilities
inferred← citeshttps://doi.org/10.1109/ipdps.2011.141openalex-snapshot
Securing Boot of an Embedded Linux on FPGA
inferred← citeshttps://doi.org/10.1109/isai.2016.0045openalex-snapshot
A Survey on the Studies of Security Guard Technology for Memory
inferred← citeshttps://doi.org/10.1109/isca.2005.22openalex-snapshot
Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions
inferred← citeshttps://doi.org/10.1109/isca.2018.00058openalex-snapshot
Mobilizing the Micro-Ops: Exploiting Context Sensitive Decoding for Security and Energy Efficiency
inferred← citeshttps://doi.org/10.1109/isca66397.2026.00046openalex-snapshot
LÆGIS: Pinpointing and Addressing Performance Overheads of GPU-Based Confidential Computing
inferred← citeshttps://doi.org/10.1109/isias.2010.5604197openalex-snapshot
Detecting memory spoofing in secure embedded systems using cache-aware FPGA guards
inferred← citeshttps://doi.org/10.1109/ispass.2018.00012openalex-snapshot
MAPS: Understanding Metadata Access Patterns in Secure Memory
inferred← citeshttps://doi.org/10.1109/ispass69572.2026.00071openalex-snapshot
Characterizing and Optimizing Cache Placement for Secure Memory Metadata
inferred← citeshttps://doi.org/10.1109/jiot.2018.2864513openalex-snapshot
FPGA-Based Symmetric Re-Encryption Scheme to Secure Data Processing for Cloud-Integrated Internet of Things
inferred← citeshttps://doi.org/10.1109/jiot.2023.3333203openalex-snapshot
Low-Latency PAE: Permutation-Based Address Encryption Hardware Engine for IoT Real-Time Memory Protection
inferred← citeshttps://doi.org/10.1109/micro.2003.1253207openalex-snapshot
Efficient memory integrity verification and encryption for secure processors
inferred← citeshttps://doi.org/10.1109/micro.2006.11openalex-snapshot
Authentication Control Point and Its Implications For Secure Processor Design
inferred← citeshttps://doi.org/10.1109/micro.2007.16openalex-snapshot
Using Address Independent Seed Encryption and Bonsai Merkle Trees to Make Secure Processors OS- and Performance-Friendly
inferred← citeshttps://doi.org/10.1109/micro.2014.25openalex-snapshot
Iso-X: A Flexible Architecture for Hardware-Managed Isolated Execution
inferred← citeshttps://doi.org/10.1109/micro.2014.39openalex-snapshot
A Practical Methodology for Measuring the Side-Channel Signal Available to the Attacker for Instruction-Level Events
inferred← citeshttps://doi.org/10.1109/micro.2016.7783741openalex-snapshot
PoisonIvy: Safe speculation for secure memory
inferred← citeshttps://doi.org/10.1109/micro.2018.00082openalex-snapshot
Shadow Block: Accelerating ORAM Accesses with Data Duplication
inferred← citeshttps://doi.org/10.1109/microw.2012.16openalex-snapshot
Security verification of hardware-enabled attestation protocols
inferred← citeshttps://doi.org/10.1109/nca.2004.1347805openalex-snapshot
Optimal parameter selection for efficient memory integrity verification using merkle hash trees
inferred← citeshttps://doi.org/10.1109/reconfig.2014.7032489openalex-snapshot
A hardware-assisted proof-of-concept for secure VoIP clients on untrusted operating systems
inferred← citeshttps://doi.org/10.1109/rsp.2011.5929973openalex-snapshot
Rapid single-chip secure processor prototyping on the OpenSPARC FPGA platform
inferred← citeshttps://doi.org/10.1109/samos.2017.8344637openalex-snapshot
Survey of secure processors
inferred← citeshttps://doi.org/10.1109/seed51797.2021.00016openalex-snapshot
Performance-Enhanced Integrity Verification for Large Memories
inferred← citeshttps://doi.org/10.1109/seed55351.2022.00018openalex-snapshot
SoK: Limitations of Confidential Computing via TEEs for High-Performance Compute Systems
inferred← citeshttps://doi.org/10.1109/socc46988.2019.1570564307openalex-snapshot
ITUS: A Secure RISC-V System-on-Chip
inferred← citeshttps://doi.org/10.1109/sp.2010.32openalex-snapshot
Bootstrapping Trust in Commodity Computers
inferred← citeshttps://doi.org/10.1109/sp.2013.24openalex-snapshot
PrivExec: Private Execution as an Operating System Service
inferred← citeshttps://doi.org/10.1109/sp.2015.10openalex-snapshot
VC3: Trustworthy Data Analytics in the Cloud Using SGX
inferred← citeshttps://doi.org/10.1109/srds.2015.24openalex-snapshot
Auditable Restoration of Distributed Programs
inferred← citeshttps://doi.org/10.1109/tc.2016.2595578openalex-snapshot
Bounded Auditable Restoration of Distributed Systems
inferred← citeshttps://doi.org/10.1109/tc.2017.2647955openalex-snapshot
Hardware-Based Trusted Computing Architectures for Isolation and Attestation
inferred← citeshttps://doi.org/10.1109/tc.2023.3290870openalex-snapshot
Secure Remote Attestation With Strong Key Insulation Guarantees
inferred← citeshttps://doi.org/10.1109/tc.2025.3533089openalex-snapshot
DC-ORAM: An ORAM Scheme Based on Dynamic Compression of Data Blocks and Position Map
inferred← citeshttps://doi.org/10.1109/tcad.2015.2419619openalex-snapshot
The HEROIC Framework: Encrypted Computation Without Shared Keys
inferred← citeshttps://doi.org/10.1109/tcad.2019.2948914openalex-snapshot
Fork Path: Batching ORAM Requests to Remove Redundant Memory Accesses
inferred← citeshttps://doi.org/10.1109/tdsc.2005.24openalex-snapshot
Hardware-Assisted Circumvention of Self-Hashing Software Tamper Resistance
inferred← citeshttps://doi.org/10.1109/tdsc.2016.2596287openalex-snapshot
Flexible Hardware-Managed Isolated Execution: Architecture, Software Support and Applications
inferred← citeshttps://doi.org/10.1109/tdsc.2017.2687463openalex-snapshot
Design and Implementation of the Ascend Secure Processor
inferred← citeshttps://doi.org/10.1109/tdsc.2017.2779780openalex-snapshot
Connecting the Dots: Privacy Leakage via Write-Access Patterns to the Main Memory
inferred← citeshttps://doi.org/10.1109/tdsc.2019.2933214openalex-snapshot
Secure Computing Enclaves Using FPGAs
inferred← citeshttps://doi.org/10.1109/tdsc.2020.3007066openalex-snapshot
E3X: Encrypt-Everything-Everywhere ISA eXtensions for Private Computation
inferred← citeshttps://doi.org/10.1109/tdsc.2024.3389560openalex-snapshot
Delta Counter: Bandwidth-Efficient Encryption Counter Representation for Secure GPU Memory
inferred← citeshttps://doi.org/10.1109/tifs.2016.2569062openalex-snapshot
Cryptoleq: A Heterogeneous Abstract Machine for Encrypted and Unencrypted Computation
inferred← citeshttps://doi.org/10.1109/trustcom/bigdatase/icess.2017.232openalex-snapshot
TransCrypt: Transparent Main Memory Encryption Using a Minimal ARM Hypervisor
inferred← citeshttps://doi.org/10.1109/uic-atc-scalcom.2014.15openalex-snapshot
Trust-E: A Trusted Embedded Operating System Based on the ARM Trustzone
inferred← citeshttps://doi.org/10.1142/s0218126622300057openalex-snapshot
Confidentiality and Integrity Schemes for Multicore Shared Memory Systems
inferred← citeshttps://doi.org/10.1145/1029146.1029156openalex-snapshot
Attacks and risk analysis for hardware supported software copy protection systems
inferred← citeshttps://doi.org/10.1145/1055626.1055629openalex-snapshot
Towards the issues in architectural support for protection of software execution
inferred← citeshttps://doi.org/10.1145/1055626.1055630openalex-snapshot
Protecting cryptographic keys and computations via virtual secure coprocessing
inferred← citeshttps://doi.org/10.1145/1055626.1055642openalex-snapshot
Architectural support for protecting user privacy on trusted processors
inferred← citeshttps://doi.org/10.1145/1062261.1062308openalex-snapshot
A combined hardware and software architecture for secure computing
inferred← citeshttps://doi.org/10.1145/1080695.1069971openalex-snapshot
Architecture for Protecting Critical Secrets in Microprocessors
inferred← citeshttps://doi.org/10.1145/1080695.1069972openalex-snapshot
High Efficiency Counter Mode Security Architecture via Prediction and Precomputation
inferred← citeshttps://doi.org/10.1145/1080695.1069974openalex-snapshot
Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions
inferred← citeshttps://doi.org/10.1145/1133572.1133600openalex-snapshot
Secure bootstrap is not enough
inferred← citeshttps://doi.org/10.1145/1152154.1152169openalex-snapshot
A low-cost memory remapping scheme for address bus protection
inferred← citeshttps://doi.org/10.1145/1179474.1179485openalex-snapshot
Virtual monotonic counters and count-limited objects using a TPM without a trusted OS
inferred← citeshttps://doi.org/10.1145/1242531.1242539openalex-snapshot
Accelerating memory decryption and authentication with frequent value prediction
inferred← citeshttps://doi.org/10.1145/1284680.1284683openalex-snapshot
Controlled physical random functions and applications
inferred← citeshttps://doi.org/10.1145/1314354.1314364openalex-snapshot
Offline untrusted storage with immediate detection of forking and replay attacks
inferred← citeshttps://doi.org/10.1145/1315245.1315294openalex-snapshot
Hardware-rooted trust for secure key management and transient trust
inferred← citeshttps://doi.org/10.1145/1346256.1346267openalex-snapshot
Using hypervisor to provide data secrecy for user applications on a per-page basis
inferred← citeshttps://doi.org/10.1145/1403375.1403657openalex-snapshot
Operating system controlled processor-memory bus encryption
inferred← citeshttps://doi.org/10.1145/1498690.1498691openalex-snapshot
Making secure processors OS- and performance-friendly
inferred← citeshttps://doi.org/10.1145/1867635.1867648openalex-snapshot
Separating hypervisor trusted computing base supported by hardware
inferred← citeshttps://doi.org/10.1145/1920261.1920318openalex-snapshot
A framework for testing hardware-software security architectures
inferred← citeshttps://doi.org/10.1145/2150976.2151022openalex-snapshot
Architectural support for hypervisor-secure virtualization
inferred← citeshttps://doi.org/10.1145/2155620.2155652openalex-snapshot
Architectural support for secure virtualization under a vulnerable hypervisor
inferred← citeshttps://doi.org/10.1145/2189750.2151022openalex-snapshot
Architectural support for hypervisor-secure virtualization
inferred← citeshttps://doi.org/10.1145/2248487.2151022openalex-snapshot
Architectural support for hypervisor-secure virtualization
inferred← citeshttps://doi.org/10.1145/2380403.2380414openalex-snapshot
A cost-effective tag design for memory data authentication in embedded systems
inferred← citeshttps://doi.org/10.1145/2382536.2382540openalex-snapshot
A secure processor architecture for encrypted computation on untrusted programs
showing the first 200 of 302 · page through all 302
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.