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Distributed Microarchitectural Protocols in the TRIPS Prototype Processor
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Outgoing claims: the papers this work cites, builds on, or argues with.
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Design and Implementation of the TRIPS Primary Memory System
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The design and implementation of a first-generation CELL processor
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Effective Compiler Support For Predicated Execution Using The Hyperblock
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A design space evaluation of grid processor architectures
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Effective compiler support for predicated execution using the hyperblock
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Focusing processor policies via critical-path prediction
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A design space evaluation of grid processor architectures
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Incoming claims: where this work appears in other papers’ reference lists and arguments.
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inferred← citeshttps://doi.org/10.1016/j.sysarc.2008.05.003openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/hpca.2018.00070openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00063openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/iccd.2016.7753330openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/iccsnt.2015.7490872openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/icpp.2011.77openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/icsamos.2009.5289226openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/ipdpsw.2017.50openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/isca.2008.10openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/ispass.2009.4919651openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/isvlsi.2012.44openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/iwqos.2014.6914305openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/jssc.2022.3140241openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/jssc.2024.3438758openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/l-ca.2008.7openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/mec.2013.6885462openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/micro.2007.41openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/micro.2010.13openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/micro.2016.7783752openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/mm.2007.4378782openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/ncm.2008.160openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/nocs.2007.23openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/nocs.2008.4492737openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/nocs.2009.5071477openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/sbac-pad.2008.20openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/tc.2010.256openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/tc.2013.48openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/tc.2014.2315628openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/tc.2015.2435748openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/tc.2016.2525981openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/tcad.2011.2170568openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/tpds.2007.1091openalex-snapshot
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inferred← citeshttps://doi.org/10.1109/tpds.2013.125openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/1088149.1088154openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/1345206.1345218openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/1367045.1367050openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/1508244.1508246openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/1508284.1508246openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/1839480.1839487openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/1988932.1988941openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/2133352.2133357openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/2390191.2390193openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/2528521.1508246openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/2584660openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/2633948.2633953openalex-snapshot
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inferred← citeshttps://doi.org/10.1155/2014/691865openalex-snapshot
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inferred← citeshttps://doi.org/10.11606/d.55.2011.tde-17052011-085128openalex-snapshot
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inferred← citeshttps://doi.org/10.21236/ada519578openalex-snapshot
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inferred← citeshttps://doi.org/10.25728/assa.2018.18.1.508openalex-snapshot
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inferred← citeshttps://doi.org/10.32657/10356/65486openalex-snapshot
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inferred← citeshttps://doi.org/10.4028/www.scientific.net/amr.659.169openalex-snapshot
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inferred← citeshttps://doi.org/10.47749/t/unicamp.2012.905263openalex-snapshot
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inferred← citeshttps://doi.org/10.48550/arxiv.1405.2907openalex-snapshot
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inferred← citeshttps://doi.org/10.5121/ijcnc.2018.10403openalex-snapshot
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inferred← citeshttps://doi.org/10.5555/1331699.1331707openalex-snapshot
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inferred← citeshttps://doi.org/10.5555/1331699.1331733openalex-snapshot
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inferred← citeshttps://doi.org/10.5555/3195638.3195698openalex-snapshot
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inferred← citeshttps://doi.org/10.5821/dissertation-2117-93339openalex-snapshot
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inferred← citeshttps://doi.org/10.7916/d83r0r0nopenalex-snapshot
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inferred← citeshttps://doi.org/10.7916/d88p67dzopenalex-snapshot
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