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Scaling to the end of silicon with EDGE architectures

https://doi.org/10.1109/mc.2004.65

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What this work says

Outgoing claims: the papers this work cites, builds on, or argues with.

inferredcites →https://doi.org/10.1007/978-3-540-24723-4_3openalex-snapshot

The Limits of Alias Analysis for Scalar Optimizations

inferredcites →https://doi.org/10.1109/2.612254openalex-snapshot

Baring it all to software: Raw machines

inferredcites →https://doi.org/10.1109/isca.1995.524578openalex-snapshot

Simultaneous multithreading: Maximizing on-chip parallelism

inferredcites →https://doi.org/10.1109/isca.2000.854387openalex-snapshot

Smart Memories: a modular reconfigurable architecture

inferredcites →https://doi.org/10.1109/isca.2002.1003558openalex-snapshot

The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays

inferredcites →https://doi.org/10.1109/isca.2003.1207019openalex-snapshot

Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture

inferredcites →https://doi.org/10.1109/mc.1982.1653825openalex-snapshot

Why systolic architectures?

inferredcites →https://doi.org/10.1109/micro.1992.696999openalex-snapshot

Effective Compiler Support For Predicated Execution Using The Hyperblock

inferredcites →https://doi.org/10.1109/micro.1997.645806openalex-snapshot

The multicluster architecture: reducing cycle time through partitioning

inferredcites →https://doi.org/10.1109/micro.1998.742118openalex-snapshot

A bandwidth-efficient architecture for media processing

inferredcites →https://doi.org/10.1109/micro.2003.1253204openalex-snapshot

Universal mechanisms for data-parallel architectures

inferredcites →https://doi.org/10.1145/144965.144998openalex-snapshot

Effective compiler support for predicated execution using the hyperblock

inferredcites →https://doi.org/10.1145/223982.224449openalex-snapshot

Simultaneous multithreading

inferredcites →https://doi.org/10.1145/223982.224451openalex-snapshot

Multiscalar processors

inferredcites →https://doi.org/10.1145/237090.237140openalex-snapshot

The case for a single-chip multiprocessor

inferredcites →https://doi.org/10.1145/339647.339673openalex-snapshot

Smart Memories

inferredcites →https://doi.org/10.1145/502874.502878openalex-snapshot

Parallel processing

inferredcites →https://doi.org/10.1145/545214.545218openalex-snapshot

The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays

inferredcites →https://doi.org/10.1145/859618.859667openalex-snapshot

Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture

inferredcites →https://doi.org/10.21236/ada419598openalex-snapshot

Smart Memories: A Modular Reconfigurable Architecture

inferredcites →https://doi.org/10.5555/800052.801861openalex-snapshot

Data flow languages and architectures

inferredcites →https://doi.org/10.5555/956417.956548openalex-snapshot

Universal mechanisms for data-parallel architectures

What points at this work

Incoming claims: where this work appears in other papers’ reference lists and arguments.

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Dataflow Computers: Their History and Future

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RCMP: A Reconfigurable Chip-Multiprocessor Architecture

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Enforcing Dimension-Order Routing in On-Chip Torus Networks Without Virtual Channels

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Can Multicore Processing Learn from Arithmetic Concepts?

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On-Chip Networks for Multicore Systems

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Composable Multicore Chips

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Connecting External Deduction Tools with ACL2

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Multiprocessor System-on-Chip

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Hardware Support for Efficient Resource Utilization in Manycore Processor Systems

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The Compiler of DFC: A Source Code Converter that Transform the Dataflow Code to the Multi-threaded C Code

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The Dataflow Runtime Environment of DFC

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Pasithea-1: An Energy-Efficient Self-contained CGRA with RISC-Like ISA

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A Non-blocking Multithreaded Architecture with Support for Speculative Threads

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Impact of Software Bypassing on Instruction Level Parallelism and Register File Traffic

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MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture

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Convergent Compilation Applied to Loop Unrolling

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On-Chip COMA Cache-Coherence Protocol for Microgrids of Microthreaded Cores

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Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures

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Loop-Aware Instruction Scheduling with Dynamic Contention Tracking for Tiled Dataflow Architectures

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High Performance Matrix Multiplication on Many Cores

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A Study of Cache Design in Stream Processor

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Introduction

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Hardware Architectures and Circuits

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An Evaluation of an OS-Based Coherence Scheme for Tiled CMPs

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Matrix-based streamization approach for improving locality and parallelism on FT64 stream processor

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Design and Tool Flow of Multimedia MPSoC Platforms

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What are the building blocks of nanoprocessor architecture?

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The Morphable Nanoprocessor Architecture: Reconfiguration at Runtime

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A Novel Highly Scalable Architecture with Partially Distributed Pipeline and Hardware/Software Instruction Encoding

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Novel O-GEHL Based Hyperblock Predictor for EDGE Architectures

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A Lightweight Fault-Tolerant Mechanism for Network-on-Chip

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An Efficient Multicast Router using Shared-Buffer with Packet Merging for Dataflow Architecture

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PAAG: A Polymorphic Array Architecture for Graphics and Image Processing

inferred← citeshttps://doi.org/10.1109/pact.2004.1342543openalex-snapshot

Static placement, dynamic issue (SPDI) scheduling for EDGE architectures

inferred← citeshttps://doi.org/10.1109/reconfig.2013.6732326openalex-snapshot

ReCompAc: Reconfigurable compute accelerator

inferred← citeshttps://doi.org/10.1109/reconfig.2015.7393298openalex-snapshot

Design and synthesis of reconfigurable control-flow structures for CGRA

inferred← citeshttps://doi.org/10.1109/samos.2013.6621136openalex-snapshot

Verilog-based simulation of hardware support for data-flow concurrency on multicore systems

inferred← citeshttps://doi.org/10.1109/samos.2013.6621138openalex-snapshot

Exploiting tightly-coupled cores

inferred← citeshttps://doi.org/10.1109/samos.2015.7363658openalex-snapshot

Imposing coarse-grained reconfiguration to general purpose processors

inferred← citeshttps://doi.org/10.1109/sbac-pad.2012.35openalex-snapshot

On the Efficiency of Register File versus Broadcast Interconnect for Collective Communications in Data-Parallel Hardware Accelerators

inferred← citeshttps://doi.org/10.1109/sips.2014.6986090openalex-snapshot

Efficient reconfigurable architecture for MIMD streaming execution using permutation network

inferred← citeshttps://doi.org/10.1109/soccon.2009.5398055openalex-snapshot

JavaFlow — A Java dataflow machine

inferred← citeshttps://doi.org/10.1109/ssst.2011.5753788openalex-snapshot

Calculation of core loss in a novel transformer design

inferred← citeshttps://doi.org/10.1109/tc.2013.48openalex-snapshot

Scaling Power and Performance viaProcessor Composability

inferred← citeshttps://doi.org/10.1109/tmscs.2017.2768362openalex-snapshot

A Systematic and Realistic Network-on-Chip Traffic Modeling and Generation Technique for Emerging Many-Core Systems

inferred← citeshttps://doi.org/10.1109/tpds.2006.136openalex-snapshot

Data-Driven Multithreading Using Conventional Microprocessors

inferred← citeshttps://doi.org/10.1109/tpds.2006.166openalex-snapshot

A Simple Data Transfer Technique Using Local Address for Networks-on-Chips

inferred← citeshttps://doi.org/10.1109/tpds.2008.170openalex-snapshot

Fei Teng 64 Stream Processing System: Architecture, Compiler, and Programming

inferred← citeshttps://doi.org/10.1109/tpds.2011.173openalex-snapshot

Balancing Performance and Cost in CMP Interconnection Networks

inferred← citeshttps://doi.org/10.1109/tpds.2013.125openalex-snapshot

Hybrid Dataflow/von-Neumann Architectures

inferred← citeshttps://doi.org/10.1109/tpds.2018.2819670openalex-snapshot

A Dataflow Processor as the Basis of a Tiled Polymorphic Computing Architecture with Fine-Grain Instruction Migration

inferred← citeshttps://doi.org/10.1109/tpds.2018.2822708openalex-snapshot

Triggered-Issuance and Triggered-Execution: A Control Paradigm to Minimize Pipeline Stalls in Distributed Controlled Coarse-Grained Reconfigurable Arrays

inferred← citeshttps://doi.org/10.1109/tpds.2025.3555329openalex-snapshot

DFU-E: A Dataflow Architecture for Edge DSP and AI Applications

inferred← citeshttps://doi.org/10.1109/trustcom.2013.121openalex-snapshot

Quantitative Analysis of Inter-block Dependence in Speculative Execution

inferred← citeshttps://doi.org/10.1109/tvlsi.2008.2002993openalex-snapshot

Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures

inferred← citeshttps://doi.org/10.1109/tvlsi.2016.2538284openalex-snapshot

Reducing Wire and Energy Overheads of the SMART NoC Using a Setup Request Network

inferred← citeshttps://doi.org/10.1109/vlsi-soc.2015.7314440openalex-snapshot

Exploiting scalable CGRA mapping of LU for energy efficiency using the Layers architecture

inferred← citeshttps://doi.org/10.1109/vlsi.2008.25openalex-snapshot

Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor

inferred← citeshttps://doi.org/10.1117/12.608799openalex-snapshot

Data-driven array architectures: a rebirth?

inferred← citeshttps://doi.org/10.1117/12.722077openalex-snapshot

Optimizing coarse-grain reconfigurable hardware utilization through multiprocessing: an H.264/AVC decoder example

inferred← citeshttps://doi.org/10.1117/12.821695openalex-snapshot

Cache-aware network-on-chip for chip multiprocessors

inferred← citeshttps://doi.org/10.1142/s0129626406002587openalex-snapshot

MICROTHREADING A MODEL FOR DISTRIBUTED INSTRUCTION-LEVEL CONCURRENCY

inferred← citeshttps://doi.org/10.1142/s0129626408003399openalex-snapshot

Rapid Prototyping of the Data-Driven Chip-Multiprocessor (D2-CMP) using FPGAs

inferred← citeshttps://doi.org/10.1145/1024393.1024408openalex-snapshot

Scalable selective re-execution for EDGE architectures

inferred← citeshttps://doi.org/10.1145/1037187.1024408openalex-snapshot

Scalable selective re-execution for EDGE architectures

inferred← citeshttps://doi.org/10.1145/1037947.1024408openalex-snapshot

Scalable selective re-execution for EDGE architectures

inferred← citeshttps://doi.org/10.1145/1037949.1024408openalex-snapshot

Scalable selective re-execution for EDGE architectures

inferred← citeshttps://doi.org/10.1145/1088149.1088177openalex-snapshot

Low-power, low-complexity instruction issue using compiler assistance

inferred← citeshttps://doi.org/10.1145/1168857.1168875openalex-snapshot

A spatial path scheduling algorithm for EDGE architectures

inferred← citeshttps://doi.org/10.1145/1168917.1168875openalex-snapshot

A spatial path scheduling algorithm for EDGE architectures

inferred← citeshttps://doi.org/10.1145/1168918.1168875openalex-snapshot

A spatial path scheduling algorithm for EDGE architectures

inferred← citeshttps://doi.org/10.1145/1168919.1168875openalex-snapshot

A spatial path scheduling algorithm for EDGE architectures

inferred← citeshttps://doi.org/10.1145/1250662.1250678openalex-snapshot

Rotary router

inferred← citeshttps://doi.org/10.1145/1250662.1250689openalex-snapshot

A 64-bit stream processor architecture for scientific applications

inferred← citeshttps://doi.org/10.1145/1250662.1250705openalex-snapshot

Late-binding

inferred← citeshttps://doi.org/10.1145/1273440.1250678openalex-snapshot

Rotary router

inferred← citeshttps://doi.org/10.1145/1273440.1250689openalex-snapshot

A 64-bit stream processor architecture for scientific applications

inferred← citeshttps://doi.org/10.1145/1273440.1250705openalex-snapshot

Late-binding

inferred← citeshttps://doi.org/10.1145/1345206.1345218openalex-snapshot

High performance dense linear algebra on a spatially distributed processor

inferred← citeshttps://doi.org/10.1145/1388969.1389000openalex-snapshot

Metaoptimization of the in-lining priority function for a compiler targeting a polymorphous computing architecture

inferred← citeshttps://doi.org/10.1145/1394608.1382140openalex-snapshot

Counting Dependence Predictors

inferred← citeshttps://doi.org/10.1145/1399972.1399981openalex-snapshot

Multitasking workload scheduling on flexible core chip multiprocessors

inferred← citeshttps://doi.org/10.1145/1454115.1454142openalex-snapshot

Multitasking workload scheduling on flexible-core chip multiprocessors

inferred← citeshttps://doi.org/10.1145/1508244.1508246openalex-snapshot

An evaluation of the TRIPS computer system

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Editorial review for independent work. ICSAC — the Institute for Complexity Science and Advanced Computing — runs a structured editorial panel for researchers publishing outside journals, and publishes on CiteStamp rails. Submission is free and goes through ORCID: icsacinstitute.org/submit.