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Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1016/s1383-7621(96)00123-3openalex-snapshot
A partitioned on-chip virtual cache for fast processors
inferredcites →https://doi.org/10.1023/b:supe.0000014800.27383.8fopenalex-snapshot
Dynamic Partitioning of Shared Cache Memory
inferredcites →https://doi.org/10.1109/4.509850openalex-snapshot
CACTI: an enhanced cache access and cycle time model
inferredcites →https://doi.org/10.1109/isca.2005.39openalex-snapshot
Optimizing Replication, Communication, and Capacity Allocation in CMPs
inferredcites →https://doi.org/10.1109/isca.2005.53openalex-snapshot
Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors
inferredcites →https://doi.org/10.1109/micro.2003.1253183openalex-snapshot
Distance associativity for high-performance energy-efficient non-uniform cache architectures
inferredcites →https://doi.org/10.1145/1080695.1070001openalex-snapshot
Optimizing Replication, Communication, and Capacity Allocation in CMPs
inferredcites →https://doi.org/10.1145/1095408.1095418openalex-snapshot
The Future of Microprocessors
inferredcites →https://doi.org/10.1145/371636.371687openalex-snapshot
Towards effective embedded processors in codesigns
inferredcites →https://doi.org/10.5555/1025127.1026001openalex-snapshot
Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture
inferredcites →https://doi.org/10.5555/956417.956577openalex-snapshot
Distance associativity for high-performance energy-efficient non-uniform cache architectures
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/9781119973584.ch13openalex-snapshot
Cooperative Caching for Chip Multiprocessors
inferred← citeshttps://doi.org/10.1007/978-3-031-01734-6openalex-snapshot
Multi-Core Cache Hierarchies
inferred← citeshttps://doi.org/10.1007/s10617-015-9168-7openalex-snapshot
CaPPS: cache partitioning with partial sharing for multi-core embedded systems
inferred← citeshttps://doi.org/10.1007/s11227-016-1927-0openalex-snapshot
Multi-cache resizing via greedy coordinate descent
inferred← citeshttps://doi.org/10.1109/access.2022.3151891openalex-snapshot
A Survey of Techniques for Reducing Interference in Real-Time Applications on Multicore Platforms
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Architecture of a polymorphic ASIC for interoperability across multi-mode H.264 decoders
inferred← citeshttps://doi.org/10.1109/bigdata.2016.7840762openalex-snapshot
SmartCache: Application layer caching to improve performance of large-scale memory mapping
inferred← citeshttps://doi.org/10.1109/ccgrid.2013.16openalex-snapshot
Flexible Capacity Partitioning in Many-Core Tiled CMPs
inferred← citeshttps://doi.org/10.1109/date.2010.5456936openalex-snapshot
A reconfigurable cache memory with heterogeneous banks
inferred← citeshttps://doi.org/10.1109/hpca.2009.4798260openalex-snapshot
Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches
inferred← citeshttps://doi.org/10.1109/hpca.2009.4798261openalex-snapshot
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy
inferred← citeshttps://doi.org/10.1109/hpca.2012.6169036openalex-snapshot
Cooperative partitioning: Energy-efficient cache partitioning for high-performance CMPs
inferred← citeshttps://doi.org/10.1109/hpca.2015.7056022openalex-snapshot
Talus: A simple way to remove cliffs in cache performance
inferred← citeshttps://doi.org/10.1109/hpca.2018.00019openalex-snapshot
KPart: A Hybrid Cache Partitioning-Sharing Technique for Commodity Multicores
inferred← citeshttps://doi.org/10.1109/hpca.2018.00034openalex-snapshot
GDP: Using Dataflow Properties to Accurately Estimate Interference-Free Performance at Runtime
inferred← citeshttps://doi.org/10.1109/hpcc64274.2024.00025openalex-snapshot
LazyCAT: Efficient Fine-Grained Cache Partitioning with Two Boundaries
inferred← citeshttps://doi.org/10.1109/icces.2011.6141004openalex-snapshot
Fair and adaptive online set-based cache partitioning
inferred← citeshttps://doi.org/10.1109/icpp.2015.24openalex-snapshot
Spatial Locality-Aware Cache Partitioning for Effective Cache Sharing
inferred← citeshttps://doi.org/10.1109/ipdpsw.2013.268openalex-snapshot
A Compiler Analysis to Determine Useful Cache Size for Energy Efficiency
inferred← citeshttps://doi.org/10.1109/isca.2012.6237037openalex-snapshot
Probabilistic Shared Cache Management (PriSM)
inferred← citeshttps://doi.org/10.1109/isca59077.2024.00047openalex-snapshot
Tartan: Microarchitecting a Robotic Processor
inferred← citeshttps://doi.org/10.1109/isvlsi.2013.6654659openalex-snapshot
Performance and energy efficient cache system design: Simultaneous execution of multiple applications on heterogeneous cores
inferred← citeshttps://doi.org/10.1109/micro.2014.46openalex-snapshot
Futility Scaling: High-Associativity Cache Partitioning
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00098openalex-snapshot
Blenda: Dynamically-Reconfigurable Stacked DRAM
inferred← citeshttps://doi.org/10.1109/nocs.2013.6558410openalex-snapshot
An NoC and cache hierarchy substrate to address effective virtualization and fault-tolerance
inferred← citeshttps://doi.org/10.1109/pccc.2015.7410332openalex-snapshot
A low-latency fine-grained dynamic shared cache management scheme for chip multi-processor
inferred← citeshttps://doi.org/10.1109/sc.2018.00038openalex-snapshot
Runtime-Assisted Cache Coherence Deactivation in Task Parallel Programs
inferred← citeshttps://doi.org/10.1109/sc41406.2024.00017openalex-snapshot
Hydrogen: Contention-Aware Hybrid Memory for Heterogeneous CPU-GPU Architectures
inferred← citeshttps://doi.org/10.1109/smartworld-uic-atc-scalcom-digitaltwin-pricomp-metaverse56740.2022.00119openalex-snapshot
LCP: A Lightweight Cache Partition Approach Based on Machine Learning
inferred← citeshttps://doi.org/10.1109/vlsi-soc.2013.6673277openalex-snapshot
Dynamic cache pooling for improving energy efficiency in 3D stacked multicore processors
inferred← citeshttps://doi.org/10.1109/ycict.2009.5382458openalex-snapshot
A novel cache mapping scheme for dynamic set-based cache partitioning
inferred← citeshttps://doi.org/10.1145/1150019.1136509openalex-snapshot
Cooperative Caching for Chip Multiprocessors
inferred← citeshttps://doi.org/10.1145/1250662.1250670openalex-snapshot
Virtual hierarchies to support server consolidation
inferred← citeshttps://doi.org/10.1145/1273440.1250670openalex-snapshot
Virtual hierarchies to support server consolidation
inferred← citeshttps://doi.org/10.1145/2366231.2337208openalex-snapshot
Probabilistic shared cache management (PriSM)
inferred← citeshttps://doi.org/10.1145/2480741.2480749openalex-snapshot
A survey on cache tuning from a power/energy perspective
inferred← citeshttps://doi.org/10.1145/2591635.2591662openalex-snapshot
Author retrospective for analytical cache models with applications to cache partitioning
inferred← citeshttps://doi.org/10.1145/2700247openalex-snapshot
Dynamic Cache Pooling in 3D Multicore Processors
inferred← citeshttps://doi.org/10.1145/2795229openalex-snapshot
Lowering Minimum Supply Voltage for Power-Efficient Cache Design by Exploiting Data Redundancy
inferred← citeshttps://doi.org/10.1145/2830555openalex-snapshot
A Survey on Cache Management Mechanisms for Real-Time Embedded Systems
inferred← citeshttps://doi.org/10.1145/3062394openalex-snapshot
A Survey of Techniques for Cache Partitioning in Multicore Processors
inferred← citeshttps://doi.org/10.1145/3511094openalex-snapshot
Energy Efficient Computing Systems: Architectures, Abstractions and Modeling to Techniques and Standards
inferred← citeshttps://doi.org/10.1145/3572911openalex-snapshot
ACTION: Adaptive Cache Block Migration in Distributed Cache Architectures
inferred← citeshttps://doi.org/10.11606/d.3.2011.tde-31082011-163312openalex-snapshot
Power Laws na modelagem de caches de microprocessadores.
inferred← citeshttps://doi.org/10.1587/transinf.e96.d.2514openalex-snapshot
Improving Cache Partitioning Algorithms for Pseudo-LRU Policies
inferred← citeshttps://doi.org/10.2200/s00365ed1v01y201105cac017openalex-snapshot
Multi-Core Cache Hierarchies
inferred← citeshttps://doi.org/10.26053/0h-65gq-7400openalex-snapshot
Managing data locality in future memory hierarchies using a hardware software codesign approach
inferred← citeshttps://doi.org/10.31274/etd-180810-3148openalex-snapshot
Dynamic cache reconfiguration based techniques for improving cache energy efficiency
inferred← citeshttps://doi.org/10.48550/arxiv.2007.04552openalex-snapshot
IOCA: High-Speed I/O-Aware LLC Management for Network-Centric Multi-Tenant Platform
inferred← citeshttps://doi.org/10.5555/1870926.1871128openalex-snapshot
A reconfigurable cache memory with heterogeneous banks
inferred← citeshttps://doi.org/10.5555/2523721.2523752openalex-snapshot
Jigsaw: scalable software-defined caches
inferred← citeshttps://doi.org/10.5821/dissertation-2117-105575openalex-snapshot
Power-constrained aware and latency-aware microarchitectural optimizations in many-core processors
inferred← citeshttps://doi.org/10.5821/dissertation-2117-336238openalex-snapshot
Runtime-assisted coherent caching
inferred← citeshttps://doi.org/10.5821/dissertation-2117-94566openalex-snapshot
Adaptive memory hierarchies for next generation tiled microarchitectures
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