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Application-Specific Processing on a General-Purpose Core via Transparent Instruction Set Customization
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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SimpleScalar: an infrastructure for computer system modeling
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Synthesis of application specific instruction sets
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PipeRench implementation of the Instruction Path Coprocessor
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Performance characterization of a hardware mechanism for dynamic optimization
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Processor acceleration through automated instruction set customization
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DISC: the dynamic instruction set computer
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From Sequences of Dependent Instructions to Functions
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A high-performance microarchitecture with hardware-programmable functional units
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PipeRench implementation of the instruction path coprocessor
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Putting the fill unit to work: dynamic optimizations for trace cache microprocessors
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The Transmeta Code Morphing/spl trade/ Software: using speculation, recovery, and adaptive retranslation to address real-life challenges
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Processor acceleration through automated instruction set customization
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Enhancing CGRA Efficiency Through Aligned Compute and Communication Provisioning
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CIExplorer: Microarchitecture-Aware Exploration for Tightly Integrated Custom Instruction
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Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units
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A reconfigurable array for superscalar processors
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Reconfigurable computing: toward software defined chips
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A NOVEL MRPSOC PROCESSOR FOR DISPATCH TIME CURTAILMENT
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Rapid Design Space Exploration of a Reconfigurable Instruction-Set Processor
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Static Worst-Case Execution Time Optimization using DPSO for ASIP Architecture
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A comparative study of locus and other many core architectures based on iot
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A Toolchain for Dynamic Function Off-load on CPU-FPGA Platforms
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Courier: A Toolchain for Application Acceleration on Heterogeneous Platforms
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Optimization and Mathematical Modeling in Computer Architecture
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A Mechanism for energy-efficient reuse of decoding and scheduling of x86 instruction streams
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TransRec: Improving Adaptability in Single-ISA Heterogeneous Systems with Transparent and Reconfigurable Acceleration
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AURORA: Automated Refinement of Coarse-Grained Reconfigurable Accelerators
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Design of Energy-Efficient High-Performance ASIP-DSP Platforms
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Generation of reconfigurable circuits from machine code
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Interactive Tool for Specifying Dedicated Hardware Accelerators
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An Automatic Mixed Software Hardware Pipeline Builder for CPU-FPGA Platforms
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Interactive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processor
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Design space exploration for a coarse grain accelerator
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Scalable multi-cores with improved per-core performance using off-the-critical path reconfigurable hardware
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A just-in-time customizable processor
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CHAINSAW: von-neumann accelerators to leverage fused instruction chains
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HW/SW mechanisms for instruction fusion, issue and commit in modern u-processors
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Specialization and reconfiguration of lightweight mobile processors for data-parallel applications
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