On the public citation graph
Support for High-Frequency Streaming in CMPs
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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-45937-5_14openalex-snapshot
StreamIt: A Language for Streaming Applications
inferredcites →https://doi.org/10.1109/hpca.1997.569661openalex-snapshot
An evaluation of fine-grain producer-initiated communication in cache-coherent multiprocessors
inferredcites →https://doi.org/10.1109/icpp.1993.25openalex-snapshot
A Hybrid Shared Memory/Message Passing Parallel Machine
inferredcites →https://doi.org/10.1109/icppw.2003.1240361openalex-snapshot
Software queue-based algorithms for pipelined synchronization on multiprocessors
inferredcites →https://doi.org/10.1109/isca.1988.5246openalex-snapshot
A cache-based message passing scheme for a shared-bus multiprocessor
inferredcites →https://doi.org/10.1109/isca.2005.34openalex-snapshot
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling
inferredcites →https://doi.org/10.1109/micro.1997.645830openalex-snapshot
MediaBench: a tool for evaluating and synthesizing multimedia and communications systems
inferredcites →https://doi.org/10.1109/micro.2002.1176256openalex-snapshot
Microarchitectural exploration with Liberty
inferredcites →https://doi.org/10.1109/micro.2005.13openalex-snapshot
Automatic Thread Extraction with Decoupled Software Pipelining
inferredcites →https://doi.org/10.1109/mm.2002.997877openalex-snapshot
The Raw microprocessor: a computational fabric for software circuits and general-purpose programs
inferredcites →https://doi.org/10.1109/pact.2004.1342552openalex-snapshot
Decoupled software pipelining with the synchronization array
inferredcites →https://doi.org/10.1145/1064978.1065039openalex-snapshot
Automatically partitioning packet processing applications for pipelined architectures
inferredcites →https://doi.org/10.1145/1065010.1065039openalex-snapshot
Automatically partitioning packet processing applications for pipelined architectures
inferredcites →https://doi.org/10.1145/1080695.1070004openalex-snapshot
Interconnections in Multi-Core Architectures
inferredcites →https://doi.org/10.1145/155332.155338openalex-snapshot
Integrating message-passing and shared-memory
inferredcites →https://doi.org/10.1145/195470.195494openalex-snapshot
Integration of message passing and shared memory in the Stanford FLASH multiprocessor
inferredcites →https://doi.org/10.1145/195473.195494openalex-snapshot
Integration of message passing and shared memory in the Stanford FLASH multiprocessor
inferredcites →https://doi.org/10.1145/224170.224399openalex-snapshot
Architectural mechanisms for explicit communication in shared memory multiprocessors
inferredcites →https://doi.org/10.1145/605397.605428openalex-snapshot
A stream compiler for communication-exposed architectures
inferredcites →https://doi.org/10.1145/633625.52440openalex-snapshot
A cache-based message passing scheme for a shared-bus multiprocessor
inferredcites →https://doi.org/10.1145/782814.782853openalex-snapshot
Inferential queueing and speculative push for reducing critical communication latencies
inferredcites →https://doi.org/10.5555/1025127.1026007openalex-snapshot
Decoupled Software Pipelining with the Synchronization Array
inferredcites →https://doi.org/10.5555/774861.774891openalex-snapshot
Microarchitectural exploration with Liberty
inferredcites →https://doi.org/10.5860/choice.35-6272openalex-snapshot
iWarp: anatomy of a parallel computing system
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/s10766-011-0173-6openalex-snapshot
Cache-Integrated Network Interfaces: Flexible On-Chip Communication and Synchronization for Large-Scale CMPs
inferred← citeshttps://doi.org/10.1016/j.jpdc.2013.12.009openalex-snapshot
Accelerating sequential programs on commodity multi-core processors
inferred← citeshttps://doi.org/10.1109/cgo.2007.7openalex-snapshot
Compiler-Managed Software-based Redundant Multi-Threading for Transient Fault Detection
inferred← citeshttps://doi.org/10.1109/compsym.2010.5685364openalex-snapshot
A lock-free cache-friendly software queue buffer for decoupled software pipelining
inferred← citeshttps://doi.org/10.1109/hpcsim.2015.7237079openalex-snapshot
The Batched DOACROSS loop parallelization algorithm
inferred← citeshttps://doi.org/10.1109/micro.2007.17openalex-snapshot
A Framework for Providing Quality of Service in Chip Multi-Processors
inferred← citeshttps://doi.org/10.1109/micro.2007.32openalex-snapshot
Global Multi-Threaded Instruction Scheduling
inferred← citeshttps://doi.org/10.1109/micro.2010.15openalex-snapshot
ReMAP: A Reconfigurable Heterogeneous Multicore Architecture
inferred← citeshttps://doi.org/10.1109/micro.2010.19openalex-snapshot
Scalable Speculative Parallelization on Commodity Clusters
inferred← citeshttps://doi.org/10.1109/pdcat.2009.24openalex-snapshot
Clustered Software Queue for Efficient Pipelined Multithreading
inferred← citeshttps://doi.org/10.1145/1346281.1346310openalex-snapshot
Communication optimizations for global multi-threaded instruction scheduling
inferred← citeshttps://doi.org/10.1145/1353534.1346310openalex-snapshot
Communication optimizations for global multi-threaded instruction scheduling
inferred← citeshttps://doi.org/10.1145/1353535.1346310openalex-snapshot
Communication optimizations for global multi-threaded instruction scheduling
inferred← citeshttps://doi.org/10.1145/1353536.1346310openalex-snapshot
Communication optimizations for global multi-threaded instruction scheduling
inferred← citeshttps://doi.org/10.1145/1400112.1400113openalex-snapshot
Performance scalability of decoupled software pipelining
inferred← citeshttps://doi.org/10.1145/1457255.1457258openalex-snapshot
Throughput-driven synthesis of embedded software for pipelined execution on multicore architectures
inferred← citeshttps://doi.org/10.1145/1787275.1787328openalex-snapshot
On-chip communication and synchronization mechanisms with cache-integrated network interfaces
inferred← citeshttps://doi.org/10.12681/eadd/22318openalex-snapshot
Direct communication and synchronization mechanisms in chip multiprocessors
inferred← citeshttps://doi.org/10.1504/ijhpcn.2013.056526openalex-snapshot
An automatic thread decomposition approach for pipelined multithreading
inferred← citeshttps://doi.org/10.47749/t/unicamp.2017.990921openalex-snapshot
The batched DOACROSS algorithm
inferred← citeshttps://doi.org/10.48456/tr-831openalex-snapshot
Communication for programmability and performance on multi-core processors
inferred← citeshttps://doi.org/10.5555/1331699.1331710openalex-snapshot
Penelope: The NBTI-Aware Processor
inferred← citeshttps://doi.org/10.5687/iscie.22.371openalex-snapshot
Clustered Pipelined Multithreading on Commodity Multi-Core Processors
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