On the public citation graph
Inferential queueing and speculative push for reducing critical communication latencies
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1016/0743-7315(91)90014-zopenalex-snapshot
Tolerating latency through software-controlled prefetching in shared-memory multiprocessors
inferredcites →https://doi.org/10.1109/2.55501openalex-snapshot
Synchronization algorithms for shared-memory multiprocessors
inferredcites →https://doi.org/10.1109/71.80120openalex-snapshot
The performance of spin lock alternatives for shared-memory multiprocessors
inferredcites →https://doi.org/10.1109/cmpcon.1997.584677openalex-snapshot
The evolution of the HP/Convex Exemplar
inferredcites →https://doi.org/10.1109/hpca.1997.569661openalex-snapshot
An evaluation of fine-grain producer-initiated communication in cache-coherent multiprocessors
inferredcites →https://doi.org/10.1109/hpca.1999.744359openalex-snapshot
Improving CC-NUMA performance using Instruction-based Prediction
inferredcites →https://doi.org/10.1109/hpca.2000.824348openalex-snapshot
Improving the throughput of synchronization by insertion of delays
inferredcites →https://doi.org/10.1109/iceccs.2000.873949openalex-snapshot
Proceedings 2000 International Conference on Parallel Processing
inferredcites →https://doi.org/10.1109/icpp.1994.81openalex-snapshot
Data Prefetching and Data Forwarding in Shared Memory Multiprocessors
inferredcites →https://doi.org/10.1109/icpp.1996.538562openalex-snapshot
The impact of speeding up critical sections with data prefetching and forwarding
inferredcites →https://doi.org/10.1109/pact.1997openalex-snapshot
Proceedings 1997 International Conference on Parallel Architectures and Compilation Techniques
inferredcites →https://doi.org/10.1145/103727.103729openalex-snapshot
Algorithms for scalable synchronization on shared-memory multiprocessors
inferredcites →https://doi.org/10.1145/165123.165146openalex-snapshot
Adaptive cache coherency for detecting migratory shared data
inferredcites →https://doi.org/10.1145/165123.165147openalex-snapshot
An adaptive cache coherence protocol optimized for migratory sharing
inferredcites →https://doi.org/10.1145/17356.17405openalex-snapshot
Multiprocessor cache synchronization: issues, innovations, evolution
inferredcites →https://doi.org/10.1145/195470.195490openalex-snapshot
Reactive synchronization algorithms for multiprocessors
inferredcites →https://doi.org/10.1145/195473.195490openalex-snapshot
Reactive synchronization algorithms for multiprocessors
inferredcites →https://doi.org/10.1145/279358.279363openalex-snapshot
Memory system characterization of commercial workloads
inferredcites →https://doi.org/10.1145/279358.279364openalex-snapshot
Performance characterization of a Quad Pentium Pro SMP using OLTP workloads
inferredcites →https://doi.org/10.1145/285930.285979openalex-snapshot
Lockup-free instruction fetch/prefetch cache organization
inferredcites →https://doi.org/10.1145/285930.285997openalex-snapshot
Memory consistency and event ordering in scalable shared-memory multiprocessors
inferredcites →https://doi.org/10.1145/291069.291067openalex-snapshot
Performance of database workloads on shared-memory systems with out-of-order processors
inferredcites →https://doi.org/10.1145/325164.325102openalex-snapshot
Memory consistency and event ordering in scalable shared-memory multiprocessors
inferredcites →https://doi.org/10.1145/339647.339669openalex-snapshot
Selective, accurate, and timely self-invalidation using last-touch prediction
inferredcites →https://doi.org/10.1145/356989.356991openalex-snapshot
Architecture and design of AlphaServer GS320
inferredcites →https://doi.org/10.1145/378993.378997openalex-snapshot
Architecture and design of AlphaServer GS320
inferredcites →https://doi.org/10.1145/68182.68188openalex-snapshot
Efficient synchronization primitives for large-scale cache-coherent multiprocessors
inferredcites →https://doi.org/10.1145/70082.68188openalex-snapshot
Efficient synchronization primitives for large-scale cache-coherent multiprocessors
inferredcites →https://doi.org/10.1145/773453.808203openalex-snapshot
Dynamic decentralized cache schemes for mimd parallel processors
inferredcites →https://doi.org/10.1145/800015.808203openalex-snapshot
Dynamic decentralized cache schemes for mimd parallel processors
inferredcites →https://doi.org/10.5555/224659.224690openalex-snapshot
A compiler algorithm that reduces read latency in ownership-based cache coherence protocols
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/11823285_49openalex-snapshot
Speeding-Up Synchronizations in DSM Multiprocessors
inferred← citeshttps://doi.org/10.1007/s11390-012-1207-2openalex-snapshot
Effcient Handling of Lock Hand-off in DSM Multiprocessors with Buffering Coherence Controllers
inferred← citeshttps://doi.org/10.1023/b:ijpp.0000029274.45582.a8openalex-snapshot
Inferential Queueing and Speculative Push
inferred← citeshttps://doi.org/10.1109/micro.2006.47openalex-snapshot
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