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Global Multi-Threaded Instruction Scheduling
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
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Code Partitioning in Decoupled Compilers
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A concurrent execution semantics for Parallel Program Graphs and Program Dependence Graphs
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The superblock: An effective technique for VLIW and superscalar compilation
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DSC: scheduling parallel tasks on an unbounded number of processors
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Exploring the performance potential of Itanium Processors with ILP-based scheduling
inferredcites →https://doi.org/10.1109/hpca.1998.650541openalex-snapshot
The potential for using thread-level data speculation to facilitate automatic parallelization
inferredcites →https://doi.org/10.1109/isca.1992.753303openalex-snapshot
Limits of Control Flow on Parallelism
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Field-testing IMPACT EPIC research results in itanium 2
inferredcites →https://doi.org/10.1109/micro.1998.742773openalex-snapshot
Effective cluster assignment for modulo scheduling
inferredcites →https://doi.org/10.1109/micro.2002.1176256openalex-snapshot
Microarchitectural exploration with Liberty
inferredcites →https://doi.org/10.1109/micro.2005.13openalex-snapshot
Automatic Thread Extraction with Decoupled Software Pipelining
inferredcites →https://doi.org/10.1109/micro.2006.47openalex-snapshot
Support for High-Frequency Streaming in CMPs
inferredcites →https://doi.org/10.1109/pact.2004.1342552openalex-snapshot
Decoupled software pipelining with the synchronization array
inferredcites →https://doi.org/10.1109/tc.1981.1675827openalex-snapshot
Trace Scheduling: A Technique for Global Microcode Compaction
inferredcites →https://doi.org/10.1145/113445.113466openalex-snapshot
Global instruction scheduling for superscalar machines
inferredcites →https://doi.org/10.1145/115372.115320openalex-snapshot
Efficiently computing static single assignment form and the control dependence graph
inferredcites →https://doi.org/10.1145/24039.24041openalex-snapshot
The program dependence graph and its use in optimization
inferredcites →https://doi.org/10.1145/262004.262005openalex-snapshot
Nesting of reducible and irreducible loops
inferredcites →https://doi.org/10.1145/291069.291018openalex-snapshot
Space-time scheduling of instruction-level parallelism on a raw machine
inferredcites →https://doi.org/10.1145/349299.349311openalex-snapshot
Modular interprocedural pointer analysis using access paths
inferredcites →https://doi.org/10.1145/36177.36201openalex-snapshot
A VLIW architecture for a trace scheduling compiler
inferredcites →https://doi.org/10.1145/53990.54022openalex-snapshot
Software pipelining: an effective scheduling technique for VLIW machines
inferredcites →https://doi.org/10.1145/73560.73573openalex-snapshot
On the adequacy of program dependence graphs for representing programs
inferredcites →https://doi.org/10.1145/859618.859667openalex-snapshot
Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Moody Scheduling for Speculative Parallelization
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New-Age: A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural Components
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M-IVC: Applying multiple input vectors to co-optimize aging and leakage
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Comparison of NBTI aging on adder architectures and ring oscillators in the downscaling technology nodes
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DOcyclical: A Latency-Resistant Cyclic Multi-Threading Approach for Automatic Program Parallelization
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Shared Register File Based ILP for Multicore
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Enhancing the L1 Data Cache Design to Mitigate HCI
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Facelift: Hiding and slowing down aging in multicores
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NBTI tolerant microarchitecture design in the presence of process variation
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Combating Aging with the Colt Duty Cycle Equalizer
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Task Mapping for Redundant Multithreading in Multi-Cores with Reliability and Performance Heterogeneity
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Performance Evaluation of Dynamic Speculative Multithreading with the Cascadia Architecture
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Adaptive Request Scheduling and Load Balancing for Edge Deployed Large Language Models
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Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques
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Static NBTI Reduction Using Internal Node Control
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