On the public citation graph
A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy
0 signed · 93 inferred · view as graph
Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
Is this your work? Sign in with ORCID and put your name on the
claims that are yours.
Reference health. See whether every reference in this work resolves to a
known work and none has been retracted — and get a dated CiteStamped
badge you can embed.
What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-540-30102-8_3openalex-snapshot
Efficient Victim Mechanism on Sector Cache Organization
inferredcites →https://doi.org/10.1109/hpca.2000.824338openalex-snapshot
Modified LRU policies for improving second-level cache behavior
inferredcites →https://doi.org/10.1109/hpca.2004.10015openalex-snapshot
Using Prime Numbers for Cache Indexing to Eliminate Conflict Misses
inferredcites →https://doi.org/10.1109/isca.1994.288133openalex-snapshot
Decoupled sectored caches: conciliating low tag implementation cost and low miss ratio
inferredcites →https://doi.org/10.1109/isca.2000.854398openalex-snapshot
Piranha: a scalable architecture based on single-chip multiprocessing
inferredcites →https://doi.org/10.1109/isca.2005.31openalex-snapshot
Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking
inferredcites →https://doi.org/10.1109/isca.2005.50openalex-snapshot
Temporal Streaming of Shared Memory
inferredcites →https://doi.org/10.1109/ispass.2005.1430562openalex-snapshot
Enhancing Multiprocessor Architecture Simulation Speed Using Matched-Pair Comparison
inferredcites →https://doi.org/10.1109/micro.2006.7openalex-snapshot
Adaptive Caches: Effective Shaping of Cache Behavior to Workloads
inferredcites →https://doi.org/10.1109/mm.2003.1196114openalex-snapshot
Itanium 2 processor microarchitecture
inferredcites →https://doi.org/10.1145/1028176.1006719openalex-snapshot
Adaptive Cache Compression for High-Performance Processors
inferredcites →https://doi.org/10.1145/1054943.1054945openalex-snapshot
A compressed memory hierarchy using an indirect index cache
inferredcites →https://doi.org/10.1145/1250662.1250709openalex-snapshot
Adaptive insertion policies for high performance caching
inferredcites →https://doi.org/10.1145/166955.166974openalex-snapshot
Efficient simulation of caches under optimal replacement with applications to miss characterization
inferredcites →https://doi.org/10.1145/268806.268810openalex-snapshot
The SimpleScalar tool set, version 2.0
inferredcites →https://doi.org/10.1145/285930.285998openalex-snapshot
Improving direct-mapped cache performance by the addition of a small fully-associative cache prefetch buffers
inferredcites →https://doi.org/10.1145/305138.305156openalex-snapshot
The pool of subsectors cache design
inferredcites →https://doi.org/10.1145/566470.566471openalex-snapshot
TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessors
inferredcites →https://doi.org/10.1145/859618.859642openalex-snapshot
Using destination-set prediction to improve the latency/bandwidth tradeoff in shared-memory multiprocessors
inferredcites →https://doi.org/10.1147/sj.52.0078openalex-snapshot
A study of replacement algorithms for a virtual-storage computer
inferredcites →https://doi.org/10.1147/sj.71.0015openalex-snapshot
Structural aspects of the System/360 Model 85, II: The cache
inferredcites →https://doi.org/10.1147/sj.92.0078openalex-snapshot
Evaluation techniques for storage hierarchies
inferredcites →https://doi.org/10.5555/956417.956577openalex-snapshot
Distance associativity for high-performance energy-efficient non-uniform cache architectures
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-031-01734-6openalex-snapshot
Multi-Core Cache Hierarchies
inferred← citeshttps://doi.org/10.1007/978-981-13-2372-0_35openalex-snapshot
Role of Cache Replacement Policies in High Performance Computing Systems: A Survey
inferred← citeshttps://doi.org/10.1007/s11227-013-0900-4openalex-snapshot
DP&TB: a coherence filtering protocol for many-core chip multiprocessors
inferred← citeshttps://doi.org/10.1007/s11432-014-5175-8openalex-snapshot
Improving multiprocessor performance with fine-grain coherence bypass
inferred← citeshttps://doi.org/10.1016/j.micpro.2015.05.005openalex-snapshot
A new cache replacement algorithm for last-level caches by exploiting tag-distance correlation of cache lines
inferred← citeshttps://doi.org/10.1016/j.sysarc.2008.10.006openalex-snapshot
A framework for low energy data management in reconfigurable multi-context architectures
inferred← citeshttps://doi.org/10.1109/aspdac.2012.6164972openalex-snapshot
PRR: A low-overhead cache replacement algorithm for embedded processors
inferred← citeshttps://doi.org/10.1109/hpca.2008.4658649openalex-snapshot
Power-Efficient DRAM Speculation
inferred← citeshttps://doi.org/10.1109/hpca.2011.5749733openalex-snapshot
NUcache: An efficient multicore cache organization based on Next-Use distance
inferred← citeshttps://doi.org/10.1109/hpca.2011.5749739openalex-snapshot
Efficient data streaming with on-chip accelerators: Opportunities and challenges
inferred← citeshttps://doi.org/10.1109/hpca.2012.6168950openalex-snapshot
SCD: A scalable coherence directory with flexible sharer set encoding
inferred← citeshttps://doi.org/10.1109/hpca.2016.7446089openalex-snapshot
Selective GPU caches to eliminate CPU-GPU HW cache coherence
inferred← citeshttps://doi.org/10.1109/hpca.2017.25openalex-snapshot
A Split Cache Hierarchy for Enabling Data-Oriented Optimizations
inferred← citeshttps://doi.org/10.1109/hpca51647.2021.00060openalex-snapshot
Stream Floating: Enabling Proactive and Decentralized Cache Optimizations
inferred← citeshttps://doi.org/10.1109/hpca53966.2022.00032openalex-snapshot
Near-Stream Computing: General and Transparent Near-Cache Acceleration
inferred← citeshttps://doi.org/10.1109/hpcc-smartcity-dss.2016.0117openalex-snapshot
AHRC: An Optimized Cache Associativity
inferred← citeshttps://doi.org/10.1109/iccd.2008.4751933openalex-snapshot
Re-examining cache replacement policies
inferred← citeshttps://doi.org/10.1109/iccd.2010.5647594openalex-snapshot
Improving cache performance by combining cost-sensitivity and locality principles in cache replacement algorithms
inferred← citeshttps://doi.org/10.1109/iccd.2017.60openalex-snapshot
DAAIP: Deadblock Aware Adaptive Insertion Policy for High Performance Caching
inferred← citeshttps://doi.org/10.1109/iccd46524.2019.00022openalex-snapshot
Bandwidth-Aware Last-Level Caching: Efficiently Coordinating Off-Chip Read and Write Bandwidth
inferred← citeshttps://doi.org/10.1109/iccit.2010.5711103openalex-snapshot
Partitioning mechanism based on dynamic Allocation of Data entries for chip multiprocessors
inferred← citeshttps://doi.org/10.1109/icicta.2011.582openalex-snapshot
SLRF: A High-efficiency Shared Less Reused Filter in Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/icpp.2013.70openalex-snapshot
Temporal-Aware Mechanism to Detect Private Data in Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/icsamos.2009.5289241openalex-snapshot
Instruction-based reuse-distance prediction for effective cache management
inferred← citeshttps://doi.org/10.1109/iiswc.2013.6704665openalex-snapshot
Characterizing multi-threaded applications for designing sharing-aware last-level cache replacement policies
inferred← citeshttps://doi.org/10.1109/interact.2012.6339621openalex-snapshot
Enhancing LRU replacement via phantom associativity
inferred← citeshttps://doi.org/10.1109/isca.2014.6853203openalex-snapshot
Navigating the cache hierarchy with a single lookup
inferred← citeshttps://doi.org/10.1109/isca.2018.00020openalex-snapshot
Rethinking Belady's Algorithm to Accommodate Prefetching
inferred← citeshttps://doi.org/10.1109/isca45697.2020.00025openalex-snapshot
Efficiently Supporting Dynamic Task Parallelism on Heterogeneous Cache-Coherent Systems
inferred← citeshttps://doi.org/10.1109/micro.2008.4771777openalex-snapshot
Virtual tree coherence: Leveraging regions and in-network multicast trees for scalable cache coherence
inferred← citeshttps://doi.org/10.1109/micro.2008.4771796openalex-snapshot
Reducing the harmful effects of last-level cache polluters with an OS-level, software-only pollute buffer
inferred← citeshttps://doi.org/10.1109/micro.2012.43openalex-snapshot
Improving Cache Management Policies Using Dynamic Reuse Distances
inferred← citeshttps://doi.org/10.1109/nas.2014.43openalex-snapshot
iCHAT: Inter-cache Hardware-Assistant Data Transfer for Heterogeneous Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/pacrim.2009.5291238openalex-snapshot
Teaching old caches new tricks: RegionTracker and predictor virtualization
inferred← citeshttps://doi.org/10.1109/pact.2011.21openalex-snapshot
DeNovo: Rethinking the Memory Hierarchy for Disciplined Parallelism
inferred← citeshttps://doi.org/10.1109/pact.2013.6618826openalex-snapshot
Generating efficient data movement code for heterogeneous architectures with distributed-memory
inferred← citeshttps://doi.org/10.1109/samos.2012.6404165openalex-snapshot
Counting stream registers: An efficient and effective snoop filter architecture
inferred← citeshttps://doi.org/10.1109/tc.2011.197openalex-snapshot
Exploiting Core Working Sets to Filter the L1 Cache with Random Sampling
inferred← citeshttps://doi.org/10.1109/tc.2011.241openalex-snapshot
Increasing the Effectiveness of Directory Caches by Avoiding the Tracking of Noncoherent Memory Blocks
inferred← citeshttps://doi.org/10.1109/tc.2015.2435790openalex-snapshot
Building Expressive and Area-Efficient Directories with Hybrid Representation and Adaptive Multi-Granular Tracking
inferred← citeshttps://doi.org/10.1109/tc.2017.2676768openalex-snapshot
Adaptive Coherence Granularity for Multi-Socket Systems
inferred← citeshttps://doi.org/10.1145/1787275.1787316openalex-snapshot
Where replacement algorithms fail
inferred← citeshttps://doi.org/10.1145/1815961.1815971openalex-snapshot
High performance cache replacement using re-reference interval prediction (RRIP)
inferred← citeshttps://doi.org/10.1145/1816038.1815971openalex-snapshot
High performance cache replacement using re-reference interval prediction (RRIP)
inferred← citeshttps://doi.org/10.1145/2019608.2019613openalex-snapshot
Dynamic access distance driven cache replacement
inferred← citeshttps://doi.org/10.1145/2370816.2370862openalex-snapshot
Optimal bypass monitor for high performance last-level caches
inferred← citeshttps://doi.org/10.1145/2677956openalex-snapshot
Mitigating Prefetcher-Caused Pollution Using Informed Caching Policies for Prefetched Blocks
inferred← citeshttps://doi.org/10.1145/2818374openalex-snapshot
Reuse Distance-Based Probabilistic Cache Replacement
inferred← citeshttps://doi.org/10.1145/3017992openalex-snapshot
Some Mathematical Facts About Optimal Cache Replacement
inferred← citeshttps://doi.org/10.11606/d.3.2011.tde-31082011-163312openalex-snapshot
Power Laws na modelagem de caches de microprocessadores.
inferred← citeshttps://doi.org/10.1587/transinf.e96.d.124openalex-snapshot
Adaptive Insertion and Promotion Policies Based on Least Recently Used Replacement
inferred← citeshttps://doi.org/10.2200/s00365ed1v01y201105cac017openalex-snapshot
Multi-Core Cache Hierarchies
inferred← citeshttps://doi.org/10.4304/jcp.7.5.1236-1243openalex-snapshot
Adaptive Capacity Sharing through Probabilistic Controlled Placement
inferred← citeshttps://doi.org/10.48550/arxiv.1808.05024openalex-snapshot
Making Belady-Inspired Replacement Policies More Effective Using Expected Hit Count
Editorial review for independent work. ICSAC — the Institute for Complexity
Science and Advanced Computing — runs a structured editorial panel for researchers
publishing outside journals, and publishes on CiteStamp rails. Submission is free
and goes through ORCID: icsacinstitute.org/submit.