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Improving Cache Management Policies Using Dynamic Reuse Distances
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1016/0020-0190(83)90034-0openalex-snapshot
Minimization of demand paging for the LRU stack model of program behavior
inferredcites →https://doi.org/10.1109/hpca.2011.5749733openalex-snapshot
NUcache: An efficient multicore cache organization based on Next-Use distance
inferredcites →https://doi.org/10.1109/iccd.2007.4601909openalex-snapshot
Cache replacement based on reuse-distance prediction
inferredcites →https://doi.org/10.1109/icsamos.2009.5289241openalex-snapshot
Instruction-based reuse-distance prediction for effective cache management
inferredcites →https://doi.org/10.1109/micro.1995.476816openalex-snapshot
A modified approach to data cache management
inferredcites →https://doi.org/10.1109/micro.2006.49openalex-snapshot
Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches
inferredcites →https://doi.org/10.1109/micro.2007.14openalex-snapshot
A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy
inferredcites →https://doi.org/10.1109/micro.2007.25openalex-snapshot
Emulating Optimal Replacement with a Shepherd Cache
inferredcites →https://doi.org/10.1109/micro.2007.42openalex-snapshot
Scavenger: A New Last Level Cache Architecture with Global Block Priority
inferredcites →https://doi.org/10.1109/micro.2008.4771793openalex-snapshot
Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency
inferredcites →https://doi.org/10.1109/micro.2010.24openalex-snapshot
Sampling Dead Block Prediction for Last-Level Caches
inferredcites →https://doi.org/10.1109/micro.2010.52openalex-snapshot
Achieving Non-Inclusive Cache Performance with Inclusive Caches: Temporal Locality Aware (TLA) Cache Management Policies
inferredcites →https://doi.org/10.1109/tc.2007.70816openalex-snapshot
Counter-Based Cache Replacement and Bypassing Algorithms
inferredcites →https://doi.org/10.1145/1006209.1006213openalex-snapshot
Inter-reference gap distribution replacement
inferredcites →https://doi.org/10.1145/1250662.1250709openalex-snapshot
Adaptive insertion policies for high performance caching
inferredcites →https://doi.org/10.1145/1454115.1454145openalex-snapshot
Adaptive insertion policies for managing shared caches
inferredcites →https://doi.org/10.1145/1669112.1669165openalex-snapshot
Comparing cache architectures and coherency protocols on x86-64 multicore SMP systems
inferredcites →https://doi.org/10.1145/1815961.1815971openalex-snapshot
High performance cache replacement using re-reference interval prediction (RRIP)
inferredcites →https://doi.org/10.1145/1854273.1854286openalex-snapshot
Accelerating multicore reuse distance analysis with sampling and parallelization
inferredcites →https://doi.org/10.1145/2000064.2000075openalex-snapshot
Bypass and insertion algorithms for exclusive last-level caches
inferredcites →https://doi.org/10.1145/2019608.2019613openalex-snapshot
Dynamic access distance driven cache replacement
inferredcites →https://doi.org/10.1145/223586.223620openalex-snapshot
An inter-reference gap model for temporal locality in program behavior
inferredcites →https://doi.org/10.1145/223587.223620openalex-snapshot
An inter-reference gap model for temporal locality in program behavior
inferredcites →https://doi.org/10.1147/sj.52.0078openalex-snapshot
A study of replacement algorithms for a virtual-storage computer
inferredcites →https://doi.org/10.5555/1331699.1331736openalex-snapshot
Scavenger: A New Last Level Cache Architecture with Global Block Priority
inferredcites →https://doi.org/10.5555/225160.225177openalex-snapshot
A modified approach to data cache management
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Design of Shared Storage Based on Cache Decouple
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SysMon: Monitoring Memory Behaviors via OS Approach
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A Study on L1 Data Cache Bypassing Methods for High-Performance GPUs
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TDC: Pool-Level Object Cache Replacement Algorithm Based on Temperature Density
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Memory-aware TLP throttling and cache bypassing for GPUs
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CCAP: A Cache Contention-Aware Virtual Machine Placement Approach for HPC Cloud
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Modeling Remapping Based Fault Tolerance Techniques for Chip Multiprocessor Cache with Design Space Exploration
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Near-optimal replacement policies for shared caches in multicore processors
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PPT-Multicore: performance prediction of OpenMP applications using reuse profiles and analytical modeling
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Aggressive GPU cache bypassing with monolithic 3D-based NoC
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CyNAPSE: A Low-power Reconfigurable Neural Inference Accelerator for Spiking Neural Networks
inferred← citeshttps://doi.org/10.1007/s11277-024-11022-5openalex-snapshot
Leveraging Replacement Algorithm for Improved Cache Management System
inferred← citeshttps://doi.org/10.1007/s11390-014-1481-2openalex-snapshot
Retention Benefit Based Intelligent Cache Replacement
inferred← citeshttps://doi.org/10.1016/j.jpdc.2017.02.004openalex-snapshot
Dynamic and discrete cache insertion policies for managing shared last level caches in large multicores
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Application Characteristics-Aware Sporadic Cache Bypassing for high performance GPGPUs
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A survey of architectural approaches for improving GPGPU performance, programmability and heterogeneity
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Early miss prediction based periodic cache bypassing for high performance GPUs
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Improving last level shared cache performance through mobile insertion policies (MIP)
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A comprehensive survey on multi-GPU systems
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Effective Cache Management and Pollution Reduction for Online Privacy
inferred← citeshttps://doi.org/10.1016/j.sysarc.2018.09.001openalex-snapshot
Detecting the phase behavior on cache performance using the reuse distance vectors
inferred← citeshttps://doi.org/10.1016/j.sysarc.2021.101994openalex-snapshot
Improving in-memory file system reading performance by fine-grained user-space cache mechanisms
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SkipCache: application aware cache management for chip multi‐processors
inferred← citeshttps://doi.org/10.1093/comjnl/bxv112openalex-snapshot
Why Does Data Prefetching Not Work for Modern Workloads?
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A Survey of Techniques for Reducing Interference in Real-Time Applications on Multicore Platforms
inferred← citeshttps://doi.org/10.1109/asap.2019.000-2openalex-snapshot
An Adaptive Memory Management Strategy Towards Energy Efficient Machine Inference in Event-Driven Neuromorphic Accelerators
inferred← citeshttps://doi.org/10.1109/cog52621.2021.9619023openalex-snapshot
A Future-Oriented Cache Management for Mobile Games
inferred← citeshttps://doi.org/10.1109/compsac57700.2023.00022openalex-snapshot
L2 Cache Access Pattern Analysis using Static Profiling of an Application
inferred← citeshttps://doi.org/10.1109/csce60160.2023.00152openalex-snapshot
EFI: Cache Replacement Policy Using Eviction Frequency Integration
inferred← citeshttps://doi.org/10.1109/dft.2019.8875457openalex-snapshot
CORE-VR: A Coherence and Reusability Aware Low Voltage Fault Tolerant Cache in Multicore
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CAMAS: Static and Dynamic Hybrid Cache Management for CPU-FPGA Platforms
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Talus: A simple way to remove cliffs in cache performance
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Coordinated static and dynamic cache bypassing for GPUs
inferred← citeshttps://doi.org/10.1109/hpca.2016.7446065openalex-snapshot
Minimal disturbance placement and promotion
inferred← citeshttps://doi.org/10.1109/hpca.2016.7446067openalex-snapshot
Modeling cache performance beyond LRU
inferred← citeshttps://doi.org/10.1109/hpca.2016.7446096openalex-snapshot
ChargeCache: Reducing DRAM latency by exploiting row access locality
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A Split Cache Hierarchy for Enabling Data-Oriented Optimizations
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Maximizing Cache Performance Under Uncertainty
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Designing a Cost-Effective Cache Replacement Policy using Machine Learning
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Dead Page and Dead Block Predictors: Cleaning TLBs and Caches Together
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P-OPT: Practical Optimal Cache Replacement for Graph Analytics
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Effective Mimicry of Belady’s MIN Policy
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ACIC: Admission-Controlled Instruction Cache
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CARE: A Concurrency-Aware Enhanced Lightweight Cache Management Framework
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CHROME: Concurrency-Aware Holistic Cache Management Framework with Online Reinforcement Learning
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From Optimal to Practical: Efficient Micro-op Cache Replacement Policies for Data Center Applications
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Allocation of last level cache partitions through thread classification with parallel universes
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RDV: A New Method for Memory Phase Detection and Simulation Points Selection
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A hybrid approach to cache management in heterogeneous CPU-FPGA platforms
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Data placement across the cache hierarchy: Minimizing data movement with reuse-aware placement
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Ctrl-C: Instruction-Aware Control Loop Based Adaptive Cache Bypassing for GPUs
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IACM: Integrated adaptive cache management for high-performance and energy-efficient GPGPU computing
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Bandwidth-Aware Last-Level Caching: Efficiently Coordinating Off-Chip Read and Write Bandwidth
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To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches
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Pattern Based Real Time Disk Scheduling Algorithm for Virtualized Environment
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Selectively GPU Cache Bypassing for Un-Coalesced Loads
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IPKB: A New Metric for Evaluating Cache Replacement Policies
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Back to the Future: Leveraging Belady's Algorithm for Improved Cache Replacement
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Ripple: Profile-Guided Instruction Cache Replacement for Data Center Applications
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Bumper: Hinting Instruction Usefulness for Robust Unified Caches
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Enhancing Instruction Prefetching via Cache and TLB Management
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R-Max: Extending BéLáDy's MIN with Prefetching to Bound Realistic Cache Performance
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CIFR: A complete in-place fault remapping strategy for CMP cache using dynamic reuse distance
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ReMiT: Redundancy Migration for Latency Aware Fault Tolerant Cache Design in Multicore
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Asymmetry & Locality-Aware Cache Bypass and Flush for NVM-Based Unified Persistent Memory
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Energy-Efficient Cache Management for NVM-Based IoT Systems
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Cache Replacement Policy Based on Expected Hit Count
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Adaptive Cache Management for Energy-Efficient GPU Computing
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Perceptron learning for reuse prediction
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Rethinking the Memory Hierarchy for Modern Languages
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Morpheus: Extending the Last Level Cache Capacity in GPU Systems Using Idle GPU Core Resources
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Effective Mimicry of Bélády’s MIN Policy
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Spontaneous Reload Cache: Mimicking a Larger Cache with Minimal Hardware Requirement
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DD-L1D: Improving the Decoupled L1D Efficiency for GPU Architecture
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Fine Grain Cache Partitioning Using Per-Instruction Working Blocks
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Exploiting Inter-Warp Heterogeneity to Improve GPGPU Performance
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Leeway: Addressing Variability in Dead-Block Prediction for Last-Level Caches
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Reducing Data Movement and Energy in Multilevel Cache Hierarchies without Losing Performance: Can you have it all?
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Warstack: Improving LLC Replacement for NVM with a Writeback-Aware Reuse Stack
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A bypass first policy for energy-efficient last level caches
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Analytical Miss Rate Calculation of L2 Cache from the RD Profile of L1 Cache
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Per-Operation Reusability Based Allocation and Migration Policy for Hybrid Cache
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MIPSGPU: Minimizing Pipeline Stalls for GPUs With Non-Blocking Execution
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Replacement Policy Adaptable Miss Curve Estimation for Efficient Cache Partitioning
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Enhancing the Malloc System with Pollution Awareness for Better Cache Performance
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Improving the Performance and Energy Efficiency of GPGPU Computing through Integrated Adaptive Cache Management
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Analytical Derivation of Concurrent Reuse Distance Profile for Multi-Threaded Application Running on Chip Multi-Processor
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Insertion and promotion for tree-based PseudoLRU last-level caches
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Block value based insertion policy for high performance last-level caches
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Adaptive Cache Bypass and Insertion for Many-core Accelerators
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Mitigating Prefetcher-Caused Pollution Using Informed Caching Policies for Prefetched Blocks
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Efficient utilization of GPGPU cache hierarchy
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Locality-Driven Dynamic GPU Cache Bypassing
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Runtime-driven shared last-level cache management for task-parallel programs
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Reuse Distance-Based Probabilistic Cache Replacement
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A model-driven approach to warp/thread-block level GPU cache bypassing
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Application-specific quantum for multi-core platform scheduler
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Exploiting Dynamic Reuse Probability to Manage Shared Last-level Caches in CPU-GPU Heterogeneous Processors
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Hardware support for protective and collaborative cache sharing
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Mitigating performance unpredictability in the IaaS using the Kyoto principle
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A Survey of Techniques for Cache Partitioning in Multicore Processors
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Access Pattern-Aware Cache Management for Improving Data Utilization in GPU
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Multiperspective reuse prediction
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Access Pattern-Aware Cache Management for Improving Data Utilization in GPU
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Improving First Level Cache Efficiency for GPUs Using Dynamic Line Protection
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Hardware support for protective and collaborative cache sharing
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Quantifying Data Locality in Dynamic Parallelism in GPUs
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Quantifying Data Locality in Dynamic Parallelism in GPUs
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Writeback-Aware Caching (Brief Announcement)
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Applying Deep Learning to the Cache Replacement Problem
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CLAM: Compiler Lease of Cache Memory
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PPT-SASMM: Scalable Analytical Shared Memory Model
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Uniform lease vs. LRU cache: analysis and evaluation
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ReuseTracker : Fast Yet Accurate Multicore Reuse Distance Analyzer
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CARL: Compiler Assigned Reference Leasing
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Blast from the Past: Least Expected Use (LEU) Cache Replacement with Statistical History
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Cache Programming for Scientific Loops Using Leases
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P4LRU: Towards An LRU Cache Entirely in Programmable Data Plane
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GMT: GPU Orchestrated Memory Tiering for the Big Data Era
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COBRRA: COntention-aware cache Bypass with Request-Response Arbitration
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Instruction-Aware Cooperative TLB and Cache Replacement Policies
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BIZA: Design of Self-Governing Block-Interface ZNS AFA for Endurance and Performance
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Light-weight Cache Replacement for Instruction Heavy Workloads
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Garibaldi: A Pairwise Instruction-Data Management for Enhancing Shared Last-Level Cache Performance in Server Workloads
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A TRRIP Down Memory Lane: Temperature-Based Re-Reference Interval Prediction For Instruction Caching
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A virtual memory manager optimized for node-level cooperative multi-tasking in memory constrained systems
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Techniques for Shared Resource Management in Systems with Throughput Processors
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ADDP: The Data Prefetching Protocol for Monitoring Capacity Misses
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Applying SVM to data bypass prediction in multi core last-level caches
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A DVFS-aware cache bypassing technique for multiple clock domain mobile SoCs
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IP-aware cache partition and replacement scheme for mobile computing devices
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Reuse distance-based shared LLC management mechanism for heterogeneous CPU-GPU systems
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Scrutinizing Resource Utilization for High Performance and Low Energy Computation
inferred← citeshttps://doi.org/10.2200/s00922ed1v01y201905cac047openalex-snapshot
Cache Replacement Policies
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LSTM-CRP: Algorithm-Hardware Co-Design and Implementation of Cache Replacement Policy Using Long Short-Term Memory
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A Survey of Cache Bypassing Techniques
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ACR: APPLICATION AWARE CACHE REPLACEMENT FOR SHARED CACHES IN MULTI-CORE SYSTEMS
inferred← citeshttps://doi.org/10.3906/elk-1610-336openalex-snapshot
Last level cache partitioning via multiverse thread classification
inferred← citeshttps://doi.org/10.48550/arxiv.1609.07234openalex-snapshot
Reducing DRAM Access Latency by Exploiting DRAM Leakage Characteristics and Common Access Patterns
inferred← citeshttps://doi.org/10.48550/arxiv.1907.12666openalex-snapshot
Modeling Shared Cache Performance of OpenMP Programs using Reuse Distance
inferred← citeshttps://doi.org/10.48550/arxiv.2012.04105openalex-snapshot
The Tribes of Machine Learning and the Realm of Computer Architecture
inferred← citeshttps://doi.org/10.48550/arxiv.2109.04621openalex-snapshot
An Effective Early Multi-core System Shared Cache Design Method Based on Reuse-distance Analysis
inferred← citeshttps://doi.org/10.5555/3195638.3195641openalex-snapshot
Perceptron learning for reuse prediction
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