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Scavenger: A New Last Level Cache Architecture with Global Block Priority
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1016/j.scico.2005.07.004openalex-snapshot
Phase-based visualization and analysis of Java programs
inferredcites →https://doi.org/10.1080/00031305.1978.10479236openalex-snapshot
Variations of Box Plots
inferredcites →https://doi.org/10.1109/40.491460openalex-snapshot
The Mips R10000 superscalar microprocessor
inferredcites →https://doi.org/10.1109/hpca.2001.903254openalex-snapshot
JETTY: filtering snoops for reduced energy consumption in SMP servers
inferredcites →https://doi.org/10.1109/isca.1990.134547openalex-snapshot
Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
inferredcites →https://doi.org/10.1109/isca.2000.854380openalex-snapshot
Wattch: a framework for architectural-level power analysis and optimizations
inferredcites →https://doi.org/10.1109/isca.2002.1003579openalex-snapshot
Timekeeping in the memory system: predicting and optimizing memory behavior
inferredcites →https://doi.org/10.1109/isca.2005.42openalex-snapshot
RegionScout: Exploiting Coarse Grain Sharing in Snoop-Based Coherence
inferredcites →https://doi.org/10.1109/lpe.2006.4271845openalex-snapshot
L-CBF: A Low-Power, Fast Counting Bloom Filter Architecture
inferredcites →https://doi.org/10.1109/mascot.2005.34openalex-snapshot
Improved estimation for software multiplexing of performance counters
inferredcites →https://doi.org/10.1109/micro.2003.1253246openalex-snapshot
Checkpoint processing and recovery: towards scalable large instruction window processors
inferredcites →https://doi.org/10.1109/tnet.2007.892882openalex-snapshot
Pipelined Heap (Priority Queue) Management for Advanced Scheduling in High-Speed Networks
inferredcites →https://doi.org/10.1145/1088149.1088163openalex-snapshot
Online performance analysis by statistical sampling of microprocessor performance counters
inferredcites →https://doi.org/10.1145/1094811.1094834openalex-snapshot
Automating vertical profiling
inferredcites →https://doi.org/10.1145/1176760.1176783openalex-snapshot
Reducing energy of virtual cache synonym lookup using bloom filters
inferredcites →https://doi.org/10.1145/1250662.1250709openalex-snapshot
Adaptive insertion policies for high performance caching
inferredcites →https://doi.org/10.1145/2591635.2667183openalex-snapshot
Bloom filtering cache misses for accurate data speculation and prefetching
inferredcites →https://doi.org/10.1145/277044.277226openalex-snapshot
Power considerations in the design of the Alpha 21264 microprocessor
inferredcites →https://doi.org/10.1145/285930.285998openalex-snapshot
Improving direct-mapped cache performance by the addition of a small fully-associative cache prefetch buffers
inferredcites →https://doi.org/10.1145/342001.339660openalex-snapshot
A fully associative software-managed cache design
inferredcites →https://doi.org/10.1145/351397.351408openalex-snapshot
Overcoming the challenges to feedback-directed optimization (Keynote Talk)
inferredcites →https://doi.org/10.1145/362686.362692openalex-snapshot
Space/time trade-offs in hash coding with allowable errors
inferredcites →https://doi.org/10.1145/514216.514219openalex-snapshot
Bloom filtering cache misses for accurate data speculation and prefetching
inferredcites →https://doi.org/10.1145/545214.545239openalex-snapshot
Timekeeping in the memory system
inferredcites →https://doi.org/10.1145/582419.582432openalex-snapshot
Online feedback-directed optimization of Java
inferredcites →https://doi.org/10.1145/605397.605403openalex-snapshot
Automatically characterizing large scale program behavior
inferredcites →https://doi.org/10.5555/370049.370424openalex-snapshot
A Scalable Cross-Platform Infrastructure for Application Performance Tuning Using Hardware Counters
inferredcites →https://doi.org/10.5555/956417.956554openalex-snapshot
Checkpoint processing and recovery: towards scalable large instruction window processors
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Accurate and Complete Hardware Profiling for OpenMP
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Data Similarity-Aware Computation Infrastructure for the Cloud
inferred← citeshttps://doi.org/10.1007/s11227-020-03533-2openalex-snapshot
Application-specific feature selection and clustering approach with HPC system profiling data
inferred← citeshttps://doi.org/10.1109/cluster49012.2020.00015openalex-snapshot
NeoMPX: Characterizing and Improving Estimation of Multiplexing Hardware Counters for PAPI
inferred← citeshttps://doi.org/10.1109/dcabes.2014.42openalex-snapshot
A Quantitative Analysis about the Cache Set-Level Utilization
inferred← citeshttps://doi.org/10.1109/hipc.2010.5713184openalex-snapshot
Reducing capacity and conflict misses using Set Saturation Levels
inferred← citeshttps://doi.org/10.1109/hpca.2011.5749733openalex-snapshot
NUcache: An efficient multicore cache organization based on Next-Use distance
inferred← citeshttps://doi.org/10.1109/hpca56546.2023.10071033openalex-snapshot
ACIC: Admission-Controlled Instruction Cache
inferred← citeshttps://doi.org/10.1109/hpcc-smartcity-dss.2016.0117openalex-snapshot
AHRC: An Optimized Cache Associativity
inferred← citeshttps://doi.org/10.1109/iccd.2014.6974670openalex-snapshot
ReMAP: Reuse and memory access cost aware eviction policy for last level cache management
inferred← citeshttps://doi.org/10.1109/iccd.2017.85openalex-snapshot
Sharing-Aware Efficient Private Caching in Many-Core Server Processors
inferred← citeshttps://doi.org/10.1109/iccd46524.2019.00022openalex-snapshot
Bandwidth-Aware Last-Level Caching: Efficiently Coordinating Off-Chip Read and Write Bandwidth
inferred← citeshttps://doi.org/10.1109/icpads.2010.79openalex-snapshot
Performance Data Extrapolation in Parallel Codes
inferred← citeshttps://doi.org/10.1109/icpads.2012.18openalex-snapshot
Performance Evaluation of Concurrent Lock-free Data Structures on GPUs
inferred← citeshttps://doi.org/10.1109/iiswc.2008.4636099openalex-snapshot
Can hardware performance counters be trusted?
inferred← citeshttps://doi.org/10.1109/ispass.2008.4510746openalex-snapshot
Next-Generation Performance Counters: Towards Monitoring Over Thousand Concurrent Events
inferred← citeshttps://doi.org/10.1109/ispass.2009.4919635openalex-snapshot
Accuracy of performance counter measurements
inferred← citeshttps://doi.org/10.1109/ispass.2015.7095789openalex-snapshot
Self-monitoring overhead of the Linux perf_ event performance counter interface
inferred← citeshttps://doi.org/10.1109/micro.2010.20openalex-snapshot
The ZCache: Decoupling Ways and Associativity
inferred← citeshttps://doi.org/10.1109/micro.2012.43openalex-snapshot
Improving Cache Management Policies Using Dynamic Reuse Distances
inferred← citeshttps://doi.org/10.1109/micro.2018.00056openalex-snapshot
CounterMiner: Mining Big Performance Data from Hardware Counters
inferred← citeshttps://doi.org/10.1109/pact.2011.21openalex-snapshot
DeNovo: Rethinking the Memory Hierarchy for Disciplined Parallelism
inferred← citeshttps://doi.org/10.1109/sbac-pad.2010.21openalex-snapshot
A Cache Replacement Policy Using Adaptive Insertion and Re-reference Prediction
inferred← citeshttps://doi.org/10.1109/tc.2013.111openalex-snapshot
Data Similarity-Aware Computation Infrastructure for the Cloud
inferred← citeshttps://doi.org/10.1109/tc.2015.2455978openalex-snapshot
A Hybrid Non-Volatile Cache Design for Solid-State Drives Using Comprehensive I/O Characterization
inferred← citeshttps://doi.org/10.1109/tc.2018.2796067openalex-snapshot
Performance and Power-Efficient Design of Dense Non-Volatile Cache in CMPs
inferred← citeshttps://doi.org/10.1109/tcad.2014.2387856openalex-snapshot
Wavelet-Based Trace Alignment Algorithms for Heterogeneous Architectures
inferred← citeshttps://doi.org/10.1109/tcad.2026.3657994openalex-snapshot
Homonoia: Reinventing Underutilized Cross-Level Cache Resource Using Reinforcement Learning
inferred← citeshttps://doi.org/10.1109/tpds.2017.2657512openalex-snapshot
Dynamic Associativity Management in Tiled CMPs by Runtime Adaptation of Fellow Sets
inferred← citeshttps://doi.org/10.1145/3445814.3446739openalex-snapshot
BayesPerf: minimizing performance monitoring errors using Bayesian statistics
inferred← citeshttps://doi.org/10.1587/transele.e94.c.468openalex-snapshot
A Novel Cache Replacement Policy via Dynamic Adaptive Insertion and Re-Reference Prediction
inferred← citeshttps://doi.org/10.4018/ijertcs.289202openalex-snapshot
Effectiveness Evaluation of Replacement Policies for On-Chip Caches in Multiprocessors
inferred← citeshttps://doi.org/10.4995/thesis/10251/32663openalex-snapshot
Hybrid caches: design and data management
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