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The ZCache: Decoupling Ways and Associativity
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-642-04128-0_1openalex-snapshot
Some Open Questions Related to Cuckoo Hashing
inferredcites →https://doi.org/10.1109/12.40842openalex-snapshot
Evaluating associativity in CPU caches
inferredcites →https://doi.org/10.1109/40.621212openalex-snapshot
Two fast and high-associativity cache schemes
inferredcites →https://doi.org/10.1109/hoti.2008.27openalex-snapshot
An Efficient Hardware-Based Multi-hash Scheme for High Speed IP Lookup
inferredcites →https://doi.org/10.1109/hpca.1996.501190openalex-snapshot
Predictive sequential associative cache
inferredcites →https://doi.org/10.1109/hpca.2004.10015openalex-snapshot
Using Prime Numbers for Cache Indexing to Eliminate Conflict Misses
inferredcites →https://doi.org/10.1109/isca.1990.134547openalex-snapshot
Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
inferredcites →https://doi.org/10.1109/isca.1995.524567openalex-snapshot
Skewed associativity enhances performance predictability
inferredcites →https://doi.org/10.1109/isca.2004.1310767openalex-snapshot
Transactional memory coherence and consistency
inferredcites →https://doi.org/10.1109/isca.2006.13openalex-snapshot
Bulk Disambiguation of Speculative Threads in Multiprocessors
inferredcites →https://doi.org/10.1109/isscc.2008.4523154openalex-snapshot
A Sub-1W to 2W Low-Power IA Processor for Mobile Internet Devices and Ultra-Mobile PCs in 45nm Hi-¿ Metal Gate CMOS
inferredcites →https://doi.org/10.1109/isscc.2010.5434030openalex-snapshot
A 40nm 16-core 128-thread CMT SPARC SoC processor
inferredcites →https://doi.org/10.1109/isscc.2010.5434033openalex-snapshot
Westmere: A family of 32nm IA processors
inferredcites →https://doi.org/10.1109/isscc.2010.5434074openalex-snapshot
The implementation of POWER7TM: A highly parallel and scalable multi-core high-end server processor
inferredcites →https://doi.org/10.1109/isscc.2010.5434077openalex-snapshot
A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS
inferredcites →https://doi.org/10.1109/l-ca.2006.15openalex-snapshot
Disintermediated Active Communication
inferredcites →https://doi.org/10.1109/micro.2003.1253183openalex-snapshot
Distance associativity for high-performance energy-efficient non-uniform cache architectures
inferredcites →https://doi.org/10.1109/micro.2007.24openalex-snapshot
Implementing Signatures for Transactional Memory
inferredcites →https://doi.org/10.1109/micro.2007.30openalex-snapshot
Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow
inferredcites →https://doi.org/10.1109/micro.2007.33openalex-snapshot
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0
inferredcites →https://doi.org/10.1109/micro.2007.42openalex-snapshot
Scavenger: A New Last Level Cache Architecture with Global Block Priority
inferredcites →https://doi.org/10.1109/mm.2006.73openalex-snapshot
IPC Considered Harmful for Multiprocessor Workloads
inferredcites →https://doi.org/10.1145/1028176.1006711openalex-snapshot
Transactional Memory Coherence and Consistency
inferredcites →https://doi.org/10.1145/1150019.1136506openalex-snapshot
Bulk Disambiguation of Speculative Threads in Multiprocessors
inferredcites →https://doi.org/10.1145/1454115.1454145openalex-snapshot
Adaptive insertion policies for managing shared caches
inferredcites →https://doi.org/10.1145/1610252.1610271openalex-snapshot
The Bulk Multicore architecture for improved programmability
inferredcites →https://doi.org/10.1145/165123.165152openalex-snapshot
A case for two-way skewed-associative caches
inferredcites →https://doi.org/10.1145/1669112.1669178openalex-snapshot
Adaptive line placement with the set balancing cache
inferredcites →https://doi.org/10.1145/1815961.1815971openalex-snapshot
High performance cache replacement using re-reference interval prediction (RRIP)
inferredcites →https://doi.org/10.1145/223982.224437openalex-snapshot
Skewed associativity enhances performance predictability
inferredcites →https://doi.org/10.1145/225830.224437openalex-snapshot
Skewed associativity enhances performance predictability
inferredcites →https://doi.org/10.1145/285930.285979openalex-snapshot
Lockup-free instruction fetch/prefetch cache organization
inferredcites →https://doi.org/10.1145/285930.285998openalex-snapshot
Improving direct-mapped cache performance by the addition of a small fully-associative cache prefetch buffers
inferredcites →https://doi.org/10.1145/339647.339660openalex-snapshot
A fully associative software-managed cache design
inferredcites →https://doi.org/10.1145/342001.339660openalex-snapshot
A fully associative software-managed cache design
inferredcites →https://doi.org/10.1145/362686.362692openalex-snapshot
Space/time trade-offs in hash coding with allowable errors
inferredcites →https://doi.org/10.1145/605397.605420openalex-snapshot
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
inferredcites →https://doi.org/10.1145/800105.803400openalex-snapshot
Universal classes of hash functions (Extended Abstract)
inferredcites →https://doi.org/10.1147/sj.52.0078openalex-snapshot
A study of replacement algorithms for a virtual-storage computer
inferredcites →https://doi.org/10.5555/1331699.1331713openalex-snapshot
Implementing Signatures for Transactional Memory
inferredcites →https://doi.org/10.5555/1331699.1331736openalex-snapshot
Scavenger: A New Last Level Cache Architecture with Global Block Priority
inferredcites →https://doi.org/10.5555/956417.956577openalex-snapshot
Distance associativity for high-performance energy-efficient non-uniform cache architectures
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Lifetime Enhancement of Non-Volatile Caches by Exploiting Dynamic Associativity Management Techniques
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IE-Cache: Counteracting Eviction-Based Cache Side-Channel Attacks Through Indirect Eviction
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Principles of Secure Processor Architecture Design
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Fusion Coherence: Scalable Cache Coherence for Heterogeneous Kilo-Core System
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Cache Memory Architectures for Handling Big Data Applications: A Survey
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Detecting and Mitigating Conflict-Based Cache Side-Channel Attacks by Monitoring Ping-Pong Accesses Patterns
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DPAPC: Deterministic Process-Aware Partitioned Cache for Real-Time Systems
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Mosaic: A Scalable Coherence Protocol
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Scalable short-entry dual-grain coherence directories with flexible region granularity
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Efficient Utilization of Shared Caches in Multicore Architectures
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An adaptive cache coherence protocol: Trading storage for traffic
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Victim retention for reducing cache misses in tiled chip multiprocessors
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Quantifying the performance and energy efficiency of advanced cache indexing for GPGPU computing
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Exploring a Hybrid Voting-based Eviction Policy for Caches and Sparse Directories on Manycore Architectures
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A Survey of Computer Architecture Simulation Techniques and Tools
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PIR-Cache: Mitigating Conflict-Based Cache Side-Channel Attacks via Partial Indirect Replacement
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A Challenge for an Efficient AMI-based Cache System on FPGA Soft Processors
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A Quantitative Analysis about the Cache Set-Level Utilization
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A reduced overhead replacement policy for Chip Multiprocessors having victim retention
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$\mathcal{RRR}$: Rethinking Randomized Remapping for High Performance Secured NVM LLC
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Flask coherence: A morphable hybrid coherence protocol to balance energy, performance and scalability
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Quantifying sources of error in McPAT and potential impacts on architectural studies
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Modeling cache performance beyond LRU
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Near-Ideal Networks-on-Chip for Servers
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Tiny Directory: Efficient Shared Memory in Many-Core Systems with Ultra-Low-Overhead Coherence Tracking
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SWAP: Effective Fine-Grain Management of Shared Last-Level Caches with Minimum Hardware Support
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KPart: A Hybrid Cache Partitioning-Sharing Technique for Commodity Multicores
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GDP: Using Dataflow Properties to Accurately Estimate Interference-Free Performance at Runtime
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AHRC: An Optimized Cache Associativity
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V-Set Cache Design for LLC of Multi-core Processors
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Bandwidth-Aware Last-Level Caching: Efficiently Coordinating Off-Chip Read and Write Bandwidth
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HyperData: A Data Transfer Accelerator for Software Data Planes Based on Targeted Prefetching
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Performance and area aware replacement policy for GPU architecture
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Behavior Aware Data Locality for Caches
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Exploring Variation-Aware Fault-Tolerant Cache under Near-Threshold Computing
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Characterizing multi-threaded applications for designing sharing-aware last-level cache replacement policies
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Enhancing LRU replacement via phantom associativity
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DELTA: Distributed Locality-Aware Cache Partitioning for Tile-based Chip Multiprocessors
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Performance Constrained Static Energy Reduction Using Way-Sharing Target-Banks
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Towards energy-proportional datacenter memory with mobile DRAM
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Probabilistic Shared Cache Management (PriSM)
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ACCORD: Enabling Associativity for Gigascale DRAM Caches by Coordinating Way-Install and Way-Prediction
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Zero Inclusion Victim: Isolating Core Caches from Inclusive Last-level Cache Evictions
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Dynamic Associativity Management Using Fellow Sets
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Rethinking DRAM Power Modes for Energy Proportionality
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Futility Scaling: High-Associativity Cache Partitioning
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The Bunker Cache for spatio-value approximation
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HyperPlane: A Scalable Low-Latency Notification Accelerator for Software Data Planes
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Scalable and Efficient Fine-Grained Cache Partitioning with Vantage
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Vectorization past dependent branches through speculation
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HPL and DGEMM Performance Variability on the Xeon Platinum 8160 Processor
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PREDATOR: A Cache Side-Channel Attack Detector Based on Precise Event Monitoring
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Randomized Last-Level Caches Are Still Vulnerable to Cache Side-Channel Attacks! But We Can Fix It
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Crucible: Retrofitting Commodity CPUs with Vulnerabilities via Transparent Software Emulation
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CLU: Co-Optimizing Locality and Utility in Thread-Aware Capacity Management for Shared Last Level Caches
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ICCI: In-Cache Coherence Information
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ACCURATE: Accuracy Maximization for Real-Time Multicore Systems With Energy-Efficient Way-Sharing Caches
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A Hardware Approach to Fairly Balance the Inter-Thread Interference in Shared Caches
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Way Combination for an Adaptive and Scalable Coherence Directory
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Static energy reduction by performance linked dynamic cache resizing
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Targeting inter set write variation to improve the lifetime of non-volatile cache using fellow sets
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Towards a Better Cache Utilization by Selective Data Storage for CMP Last Level Caches
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V-SET CACHE: AN EFFICIENT ADAPTIVE SHARED CACHE FOR MULTI-CORE PROCESSORS
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Cache index-aware memory allocation
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Cache index-aware memory allocation
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Towards energy-proportional datacenter memory with mobile DRAM
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Probabilistic shared cache management (PriSM)
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Area-efficient near-associative memories on FPGAs
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Insertion and promotion for tree-based PseudoLRU last-level caches
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Multi-grain coherence directories
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Temporal-based multilevel correlating inclusive cache replacement
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Last-level cache deduplication
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Area-Efficient Near-Associative Memories on FPGAs
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Supporting Differentiated Services in Computers via Programmable Architecture for Resourcing-on-Demand (PARD)
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Dynamic associativity management using utility based way-sharing
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Supporting Differentiated Services in Computers via Programmable Architecture for Resourcing-on-Demand (PARD)
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Supporting Differentiated Services in Computers via Programmable Architecture for Resourcing-on-Demand (PARD)
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Large pages and lightweight memory management in virtualized environments
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Dynamic associativity enabled DNUCA to improve block localisation in tiled CMPs
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Exploiting Private Local Memories to Reduce the Opportunity Cost of Accelerator Integration
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A Software Cache Partitioning System for Hash-Based Caches
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Efficient Address Translation for Architectures with Multiple Page Sizes
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A Survey of Techniques for Cache Partitioning in Multicore Processors
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Accelerating GPU Hardware Transactional Memory with Snapshot Isolation
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Efficient Address Translation for Architectures with Multiple Page Sizes
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Accelerating GPU Hardware Transactional Memory with Snapshot Isolation
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Reducing Writebacks Through In-Cache Displacement
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CASHT: Contention Analysis in Shared Hierarchies with Thefts
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Warping cache simulation of polyhedral programs
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ACTION: Adaptive Cache Block Migration in Distributed Cache Architectures
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MVC: Enabling Fully Coherent Multi-Data-Views through the Memory Hierarchy with Processing in Memory
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A Cost-Effective Dueling Framework for Set-Associative Cache Indexing
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Some Practical Randomized Algorithms and Data Structures
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Studying the Impact of Multicore Processor Scaling on Cache Coherence Directories via Reuse Distance Analysis
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A Skewed Multi-banked Cache for Many-core Vector Processors
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BliMe: Verifiably Secure Outsourced Computation with Hardware-Enforced Taint Tracking
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Scrutinizing Resource Utilization for High Performance and Low Energy Computation
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Reducing miss rate in a non-inclusive cache with inclusive directory of a chip multiprocessor
inferred← citeshttps://doi.org/10.21655/ijsi.1673-7288.00249openalex-snapshot
Hybrid Access Cache Indexing Framework Adapted to GPU
inferred← citeshttps://doi.org/10.21778/2218-5453-2018-5-47-53openalex-snapshot
THE PROBLEM OF PROVIDING CACHE COHERENCE IN MULTIPROCESSOR SYSTEMS WITH MANY PROCESSORS
inferred← citeshttps://doi.org/10.2200/s00365ed1v01y201105cac017openalex-snapshot
Multi-Core Cache Hierarchies
inferred← citeshttps://doi.org/10.2200/s00864ed1v01y201807cac045openalex-snapshot
Principles of Secure Processor Architecture Design
inferred← citeshttps://doi.org/10.23919/fruct48808.2020.9087481openalex-snapshot
Fast and Scalable Simulation Framework for Large In-Order Chip Multiprocessors
inferred← citeshttps://doi.org/10.3390/a18120804openalex-snapshot
Hash Tables as Engines of Randomness at the Limits of Computation: A Unified Review of Algorithms
inferred← citeshttps://doi.org/10.3390/app131810526openalex-snapshot
QZRAM: A Transparent Kernel Memory Compression System Design for Memory-Intensive Applications with QAT Accelerator Integration
inferred← citeshttps://doi.org/10.34133/2022/9795476openalex-snapshot
ALabeledArchitecture for Low-Entropy Clouds: Theory, Practice, and Lessons
inferred← citeshttps://doi.org/10.3906/elk-1610-336openalex-snapshot
Last level cache partitioning via multiverse thread classification
inferred← citeshttps://doi.org/10.48550/arxiv.1504.04640openalex-snapshot
The Influence of Malloc Placement on TSX Hardware Transactional Memory
inferred← citeshttps://doi.org/10.48550/arxiv.1508.03087openalex-snapshot
Providing High and Controllable Performance in Multicore Systems Through Shared Resource Management
inferred← citeshttps://doi.org/10.48550/arxiv.2009.09090openalex-snapshot
MIRAGE: Mitigating Conflict-Based Cache Attacks with a Practical Fully-Associative Design
inferred← citeshttps://doi.org/10.48550/arxiv.2102.09673openalex-snapshot
Effective Cache Apportioning for Performance Isolation Under Compiler Guidance
inferred← citeshttps://doi.org/10.48550/arxiv.2109.11666openalex-snapshot
SLO beyond the Hardware Isolation Limits
inferred← citeshttps://doi.org/10.4995/thesis/10251/112423openalex-snapshot
Adaptive Prefetching and Cache Partitioning for Multicore Processors
inferred← citeshttps://doi.org/10.4995/thesis/10251/165254openalex-snapshot
Novel Cache Hierarchies with Photonic Interconnects for Chip Multiprocessors
inferred← citeshttps://doi.org/10.5075/epfl-thesis-6631openalex-snapshot
Multi-Gigabyte On-Chip DRAM Caches for Servers
inferred← citeshttps://doi.org/10.5555/2523721.2523752openalex-snapshot
Jigsaw: scalable software-defined caches
inferred← citeshttps://doi.org/10.5555/2755753.2757023openalex-snapshot
A hybrid packet/circuit-switched router to accelerate memory access in NoC-based chip multiprocessors
inferred← citeshttps://doi.org/10.5555/3195638.3195690openalex-snapshot
The bunker cache for spatio-value approximation
inferred← citeshttps://doi.org/10.5555/3291656.3291680openalex-snapshot
HPL and DGEMM performance variability on the Xeon Platinum 8160 processor
inferred← citeshttps://doi.org/10.5755/j01.itc.47.3.18433openalex-snapshot
On Improving Efficiency and Utilization of Last Level Cache in Multicore Systems
inferred← citeshttps://doi.org/10.70675/22db70b0z0f98z4fbez90cezf8c8729e2ea5openalex-snapshot
Compressed cache layout aware prefetching
inferred← citeshttps://doi.org/10.7282/t3-m0cq-tt95openalex-snapshot
Improving and complementing virtual memory using hardware techniques
inferred← citeshttps://doi.org/10.7282/t3qc073nopenalex-snapshot
Using TLB Speculation to Overcome Page Splintering in Virtual Machines
inferred← citeshttps://doi.org/10.7298/x4d50jzwopenalex-snapshot
SCALABLE DYNAMIC MULTI-RESOURCE ALLOCATION IN MULTICORE SYSTEMS
inferred← citeshttps://doi.org/10.7916/d8-a78j-z392openalex-snapshot
Scalable Emulation of Heterogeneous Systems
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