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Addressing End-to-End Memory Access Latency in NoC-Based Multicores
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1016/j.jpdc.2012.01.013openalex-snapshot
Globally Synchronized Frames for guaranteed quality-of-service in on-chip networks
inferredcites →https://doi.org/10.1109/2.982916openalex-snapshot
Simics: A full system simulation platform
inferredcites →https://doi.org/10.1109/dsn.2006.35openalex-snapshot
Exploring Fault-Tolerant Network-on-Chip Architectures
inferredcites →https://doi.org/10.1109/hpca.2001.903268openalex-snapshot
A delay model and speculative architecture for pipelined routers
inferredcites →https://doi.org/10.1109/hpca.2010.5416658openalex-snapshot
ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers
inferredcites →https://doi.org/10.1109/iccd.2007.4601881openalex-snapshot
A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS
inferredcites →https://doi.org/10.1109/isca.1990.134508openalex-snapshot
Virtual-channel flow control
inferredcites →https://doi.org/10.1109/isca.1999.765953openalex-snapshot
A performance comparison of contemporary DRAM architectures
inferredcites →https://doi.org/10.1109/isca.2001.937434openalex-snapshot
Focusing processor policies via critical-path prediction
inferredcites →https://doi.org/10.1109/isca.2004.1310774openalex-snapshot
Low-latency virtual-channel routers for on-chip networks
inferredcites →https://doi.org/10.1109/isca.2008.7openalex-snapshot
Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems
inferredcites →https://doi.org/10.1109/micro.2004.22openalex-snapshot
Memory Controller Optimizations for Web Servers
inferredcites →https://doi.org/10.1109/micro.2007.21openalex-snapshot
Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors
inferredcites →https://doi.org/10.1109/micro.2007.40openalex-snapshot
Process Variation Tolerant 3T1D-Based Cache Architectures
inferredcites →https://doi.org/10.1109/micro.2010.51openalex-snapshot
Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior
inferredcites →https://doi.org/10.1109/mm.2002.997877openalex-snapshot
The Raw microprocessor: a computational fabric for software circuits and general-purpose programs
inferredcites →https://doi.org/10.1109/mm.2006.10openalex-snapshot
Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance
inferredcites →https://doi.org/10.1109/mm.2007.4378783openalex-snapshot
A 5-GHz Mesh Interconnect for a Teraflops Processor
inferredcites →https://doi.org/10.1109/tpds.2007.1091openalex-snapshot
A NUCA Substrate for Flexible CMP Cache Sharing
inferredcites →https://doi.org/10.1145/1028176.1006717openalex-snapshot
Low-Latency Virtual-Channel Routers for On-Chip Networks
inferredcites →https://doi.org/10.1145/1105734.1105747openalex-snapshot
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
inferredcites →https://doi.org/10.1145/1186736.1186737openalex-snapshot
SPEC CPU2006 benchmark descriptions
inferredcites →https://doi.org/10.1145/1250662.1250708openalex-snapshot
Interconnect design considerations for large NUCA caches
inferredcites →https://doi.org/10.1145/1362622.1362630openalex-snapshot
Age-based packet arbitration in large-radix k -ary n -cubes
inferredcites →https://doi.org/10.1145/1394608.1382128openalex-snapshot
Parallelism-Aware Batch Scheduling
inferredcites →https://doi.org/10.1145/1394608.1382130openalex-snapshot
Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks
inferredcites →https://doi.org/10.1145/1669112.1669150openalex-snapshot
Application-aware prioritization mechanisms for on-chip networks
inferredcites →https://doi.org/10.1145/1854273.1854359openalex-snapshot
Approximating age-based arbitration in on-chip networks
inferredcites →https://doi.org/10.1145/300979.300998openalex-snapshot
A performance comparison of contemporary DRAM architectures
inferredcites →https://doi.org/10.1145/379240.379253openalex-snapshot
Focusing processor policies via critical-path prediction
inferredcites →https://doi.org/10.1145/605397.605420openalex-snapshot
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Enabling Flow Preservation and Portability in Multicore Implementations of Simulink Models
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A Log File Analysis Technique Using Binary-Based Approach
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Data access skipping for recursive partitioning methods
inferred← citeshttps://doi.org/10.1016/j.jpdc.2013.11.004openalex-snapshot
Direct distributed memory access for CMPs
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Efficient selective multicore prefetching under limited memory bandwidth
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An Efficient Log File Analysis Algorithm Using Binary-based Data Structure
inferred← citeshttps://doi.org/10.1109/access.2018.2862633openalex-snapshot
Cache Access Fairness in 3D Mesh-Based NUCA
inferred← citeshttps://doi.org/10.1109/hoti.2016.026openalex-snapshot
Exploring Wireless Technology for Off-Chip Memory Access
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Cache-Aware Approximate Computing for Decision Tree Learning
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DICE: Detailed Inter-Chiplet End-to-End Phy Modeling for Accurate Chiplet Simulation
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An application-aware heterogeneous prioritization framework for NoC based chip multiprocessors
inferred← citeshttps://doi.org/10.1109/isvlsi.2015.8openalex-snapshot
Achieving Memory Access Equalization Via Round-Trip Routing Latency Prediction in 3D Many-Core NoCs
inferred← citeshttps://doi.org/10.1109/isvlsi.2018.00028openalex-snapshot
High Bandwidth Off-Chip Memory Access Through Hybrid Switching and Inter-Chip Wireless Links
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Supporting QoS in AXI4 Based Communication Architecture
inferred← citeshttps://doi.org/10.1109/micro.2014.34openalex-snapshot
Compiler Support for Optimizing Memory Bank-Level Parallelism
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POSTER: Location-Aware Computation Mapping for Manycore Processors
inferred← citeshttps://doi.org/10.1109/pdp.2014.84openalex-snapshot
An Exploration of Page Replication for NoC-Based On-Chip Distributed Memory Systems
inferred← citeshttps://doi.org/10.1109/pdp.2016.47openalex-snapshot
A Simple Activation/Deactivation Prefetching Scheme for Chip Multiprocessors
inferred← citeshttps://doi.org/10.1109/recosoc.2013.6581525openalex-snapshot
Measuring memory access latency for software objects in a NUMA system-on-chip architecture
inferred← citeshttps://doi.org/10.1109/rtas48715.2020.00-16openalex-snapshot
Addressing Resource Contention and Timing Predictability for Multi-Core Architectures with Shared Memory Interconnects
inferred← citeshttps://doi.org/10.1109/tc.2020.2971982openalex-snapshot
Advance Virtual Channel Reservation
inferred← citeshttps://doi.org/10.1109/tcad.2021.3091410openalex-snapshot
Flexible and Efficient QoS Provisioning in AXI4-Based Network-on-Chip Architecture
inferred← citeshttps://doi.org/10.1109/tvlsi.2014.2387351openalex-snapshot
RISO: Enforce Noninterfered Performance With Relaxed Network-on-Chip Isolation in Many-Core Cloud Processors
inferred← citeshttps://doi.org/10.1109/vlsid.2014.47openalex-snapshot
NoC Scheduling for Improved Application-Aware and Memory-Aware Transfers in Multi-core Systems
inferred← citeshttps://doi.org/10.1145/3126561openalex-snapshot
Round-trip DRAM Access Fairness in 3D NoC-based Many-core Systems
inferred← citeshttps://doi.org/10.1145/3130218.3130225openalex-snapshot
Fairness-Oriented and Location-Aware NUCA for Many-Core SoC
inferred← citeshttps://doi.org/10.1145/3192366.3192386openalex-snapshot
Enhancing computation-to-core assignment with physical location information
inferred← citeshttps://doi.org/10.1145/3307650.3322212openalex-snapshot
Opportunistic computing in GPU architectures
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Co-optimizing memory-level parallelism and cache-level parallelism
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A Physical-Aware Framework for Memory Network Design Space Exploration
inferred← citeshttps://doi.org/10.1364/acpc.2017.su2a.56openalex-snapshot
SOIN: Scalable Optical Interconnect Network for On-chip Parallel Memory Access
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On-Chip Networks, Second Edition
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Advance Virtual Channel Reservation
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Adaptive Prefetching and Cache Partitioning for Multicore Processors
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