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Compiler Support for Optimizing Memory Bank-Level Parallelism
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/3-540-44587-0_1openalex-snapshot
SPEComp: A New Benchmark Suite for Measuring Parallel Computer Performance
inferredcites →https://doi.org/10.1007/978-3-642-15672-4_28openalex-snapshot
Software-Hardware Cooperative DRAM Bank Partitioning for Chip Multiprocessors
inferredcites →https://doi.org/10.1007/s11241-012-9158-9openalex-snapshot
Memory-centric scheduling for multicore hard real-time systems
inferredcites →https://doi.org/10.1016/0743-7315(92)90027-kopenalex-snapshot
Tiling multidimensional iteration spaces for multicomputers
inferredcites →https://doi.org/10.1109/71.97902openalex-snapshot
A loop transformation theory and an algorithm to maximize parallelism
inferredcites →https://doi.org/10.1109/cgo.2011.5764684openalex-snapshot
On-chip cache hierarchy-aware tile scheduling for multicore machines
inferredcites →https://doi.org/10.1109/date.2011.5763155openalex-snapshot
MLP aware heterogeneous memory system
inferredcites →https://doi.org/10.1109/hpca.2005.2openalex-snapshot
A Performance Comparison of DRAM Memory System Optimizations for SMT Processors
inferredcites →https://doi.org/10.1109/hpca.2010.5416658openalex-snapshot
ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers
inferredcites →https://doi.org/10.1109/hpca.2012.6168944openalex-snapshot
Balancing DRAM locality and parallelism in shared memory CMP systems
inferredcites →https://doi.org/10.1109/hpca.2014.6835945openalex-snapshot
Improving system throughput and fairness simultaneously in shared memory CMP systems via Dynamic Bank Partitioning
inferredcites →https://doi.org/10.1109/isca.2006.5openalex-snapshot
A Case for MLP-Aware Cache Replacement
inferredcites →https://doi.org/10.1109/isca.2008.7openalex-snapshot
Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems
inferredcites →https://doi.org/10.1109/isca.2012.6237032openalex-snapshot
A case for exploiting subarray-level parallelism (SALP) in DRAM
inferredcites →https://doi.org/10.1109/micro.2004.22openalex-snapshot
Memory Controller Optimizations for Web Servers
inferredcites →https://doi.org/10.1109/micro.2008.4771792openalex-snapshot
Mini-rank: Adaptive DRAM architecture for improving memory power efficiency
inferredcites →https://doi.org/10.1109/micro.2010.51openalex-snapshot
Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior
inferredcites →https://doi.org/10.1109/micro.2012.35openalex-snapshot
Addressing End-to-End Memory Access Latency in NoC-Based Multicores
inferredcites →https://doi.org/10.1109/pact.2009.36openalex-snapshot
Data Layout Transformation for Enhancing Data Locality on NUCA Chip Multiprocessors
inferredcites →https://doi.org/10.1109/rtas.2006.35openalex-snapshot
Real-Time Scheduling on Multicore Platforms
inferredcites →https://doi.org/10.1109/trustcom.2013.145openalex-snapshot
A Study of Leveraging Memory Level Parallelism for DRAM System on Multi-core/Many-Core Architecture
inferredcites →https://doi.org/10.1145/106972.106981openalex-snapshot
The cache performance and optimizations of blocked algorithms
inferredcites →https://doi.org/10.1145/113445.113449openalex-snapshot
A data locality optimizing algorithm
inferredcites →https://doi.org/10.1145/1150019.1136501openalex-snapshot
A Case for MLP-Aware Cache Replacement
inferredcites →https://doi.org/10.1145/1394608.1382128openalex-snapshot
Parallelism-Aware Batch Scheduling
inferredcites →https://doi.org/10.1145/1394608.1382172openalex-snapshot
Self-Optimizing Memory Controllers
inferredcites →https://doi.org/10.1145/1504176.1504209openalex-snapshot
Compiler-assisted dynamic scheduling for effective parallelization of loop nests on multicore processors
inferredcites →https://doi.org/10.1145/1654059.1654102openalex-snapshot
Future scaling of processor-memory interfaces
inferredcites →https://doi.org/10.1145/1669112.1669155openalex-snapshot
Improving memory bank-level parallelism in the presence of prefetching
inferredcites →https://doi.org/10.1145/1806596.1806605openalex-snapshot
Cache topology aware computation mapping for multicores
inferredcites →https://doi.org/10.1145/1815961.1815983openalex-snapshot
Rethinking DRAM design and organization for energy-constrained multi-cores
inferredcites →https://doi.org/10.1145/1854273.1854336openalex-snapshot
Data layout transformation exploiting memory-level parallelism in structured grid many-core applications
inferredcites →https://doi.org/10.1145/2133382.2133386openalex-snapshot
Improving System Energy Efficiency with Memory Rank Subsetting
inferredcites →https://doi.org/10.1145/2155620.2155664openalex-snapshot
Reducing memory interference in multicore systems via application-aware memory channel partitioning
inferredcites →https://doi.org/10.1145/2259016.2259044openalex-snapshot
Hierarchical overlapped tiling
inferredcites →https://doi.org/10.1145/2366231.2337202openalex-snapshot
A case for exploiting subarray-level parallelism (SALP) in DRAM
inferredcites →https://doi.org/10.1145/2370816.2370869openalex-snapshot
A software memory partition approach for eliminating bank-level interference in multicore systems
inferredcites →https://doi.org/10.1145/2451116.2451137openalex-snapshot
Regularities considered harmful
inferredcites →https://doi.org/10.1145/263699.263719openalex-snapshot
Maximizing parallelism and minimizing synchronization with affine transforms
inferredcites →https://doi.org/10.1145/360128.360134openalex-snapshot
A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality
inferredcites →https://doi.org/10.1184/r1/6468701openalex-snapshot
DRAM-Aware Last-Level Cache Writeback: Reducing Write-Caused Interference in Memory Systems
inferredcites →https://doi.org/10.5555/2190025.2190063openalex-snapshot
On-chip cache hierarchy-aware tile scheduling for multicore machines
inferredcites →https://doi.org/10.5555/2523721.2523754openalex-snapshot
Reshaping cache misses to improve row-buffer locality in multicore systems
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-030-17227-5_19openalex-snapshot
Exploiting Reconfigurable Vector Processing for Energy-Efficient Computation in 3D-Stacked Memories
inferred← citeshttps://doi.org/10.1007/978-3-319-32094-6_6openalex-snapshot
Conservative Open-Page Policy
inferred← citeshttps://doi.org/10.1109/hpca.2016.7446096openalex-snapshot
ChargeCache: Reducing DRAM latency by exploiting row access locality
inferred← citeshttps://doi.org/10.1109/iccd.2018.00051openalex-snapshot
Solar-DRAM: Reducing DRAM Access Latency by Exploiting the Variation in Local Bitlines
inferred← citeshttps://doi.org/10.1109/isca.2018.00027openalex-snapshot
A Case for Richer Cross-Layer Abstractions: Bridging the Semantic Gap with Expressive Memory
inferred← citeshttps://doi.org/10.1109/mascots.2018.00022openalex-snapshot
Quantifying and Optimizing Data Access Parallelism on Manycores
inferred← citeshttps://doi.org/10.1109/micro.2016.7783760openalex-snapshot
Improving bank-level parallelism for irregular applications
inferred← citeshttps://doi.org/10.1145/2745844.2745867openalex-snapshot
Memory Row Reuse Distance and its Role in Optimizing Application Performance
inferred← citeshttps://doi.org/10.1145/2796314.2745867openalex-snapshot
Memory Row Reuse Distance and its Role in Optimizing Application Performance
inferred← citeshttps://doi.org/10.1145/3314221.3314599openalex-snapshot
Co-optimizing memory-level parallelism and cache-level parallelism
inferred← citeshttps://doi.org/10.1145/3808297openalex-snapshot
SIMT-Step Execution: A Flexible Operational Semantics for GPU Subgroup Behavior
inferred← citeshttps://doi.org/10.48550/arxiv.1609.07234openalex-snapshot
Reducing DRAM Access Latency by Exploiting DRAM Leakage Characteristics and Common Access Patterns
inferred← citeshttps://doi.org/10.48550/arxiv.2002.12798openalex-snapshot
Optimizing Memory-Access Patterns for Deep Learning Accelerators
inferred← citeshttps://doi.org/10.5555/3195638.3195708openalex-snapshot
Improving bank-level parallelism for irregular applications
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