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Amoeba-Cache: Adaptive Blocks for Eliminating Waste in the Memory Hierarchy
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-540-92990-1_25openalex-snapshot
Revisiting Cache Block Superloading
inferredcites →https://doi.org/10.1109/hpca.2004.10010openalex-snapshot
Accurate and Complexity-Effective Spatial Pattern Prediction
inferredcites →https://doi.org/10.1109/hpca.2006.1598121openalex-snapshot
Increasing the Cache Efficiency by Eliminating Noise
inferredcites →https://doi.org/10.1109/hpca.2007.346202openalex-snapshot
Line Distillation: Increasing Cache Capacity by Filtering Unused Words in Cache Lines
inferredcites →https://doi.org/10.1109/ipdps.2006.1639646openalex-snapshot
TPCC-UVa: an open-source TPC-C implementation for parallel and distributed systems
inferredcites →https://doi.org/10.1109/ipdps.2010.5470352openalex-snapshot
Adapting cache partitioning algorithms to pseudo-LRU replacement policies
inferredcites →https://doi.org/10.1109/ipdps.2011.420openalex-snapshot
Power, Programmability, and Granularity: The Challenges of ExaScale Computing
inferredcites →https://doi.org/10.1109/isca.1995.524548openalex-snapshot
Dynamic self-invalidation: reducing coherence overhead in shared-memory multiprocessors
inferredcites →https://doi.org/10.1109/isca.1998.694794openalex-snapshot
Exploiting spatial locality in data caches using spatial footprints
inferredcites →https://doi.org/10.1109/isca.2002.1003579openalex-snapshot
Timekeeping in the memory system: predicting and optimizing memory behavior
inferredcites →https://doi.org/10.1109/isca.2012.6237047openalex-snapshot
The dynamic granularity memory system
inferredcites →https://doi.org/10.1109/micro.2007.30openalex-snapshot
Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow
inferredcites →https://doi.org/10.1109/micro.2007.33openalex-snapshot
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0
inferredcites →https://doi.org/10.1109/micro.2008.4771793openalex-snapshot
Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency
inferredcites →https://doi.org/10.1109/mm.2010.38openalex-snapshot
Power7: IBM's Next-Generation Server Processor
inferredcites →https://doi.org/10.1109/mm.2010.83openalex-snapshot
Performance and Energy Implications of Many-Core Caches for Throughput Computing
inferredcites →https://doi.org/10.1109/pact.2011.21openalex-snapshot
DeNovo: Rethinking the Memory Hierarchy for Disciplined Parallelism
inferredcites →https://doi.org/10.1145/1105734.1105747openalex-snapshot
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
inferredcites →https://doi.org/10.1145/1250662.1250709openalex-snapshot
Adaptive insertion policies for high performance caching
inferredcites →https://doi.org/10.1145/139669.139725openalex-snapshot
Adjustable block size coherent caches
inferredcites →https://doi.org/10.1145/191995.192072openalex-snapshot
Decoupled sectored caches: conciliating low tag implementation cost
inferredcites →https://doi.org/10.1145/2000064.2000100openalex-snapshot
Adaptive granularity memory systems
inferredcites →https://doi.org/10.1145/2155620.2155673openalex-snapshot
Efficiently enabling conventional block sizes for very large die-stacked DRAM caches
inferredcites →https://doi.org/10.1145/224538.224622openalex-snapshot
A data cache with multiple caching strategies tuned to different types of locality
inferredcites →https://doi.org/10.1145/2366231.2337222openalex-snapshot
The dynamic granularity memory system
inferredcites →https://doi.org/10.1145/2591635.2667170openalex-snapshot
A data cache with multiple caching strategies tuned to different types of locality
inferredcites →https://doi.org/10.1145/279358.279404openalex-snapshot
Exploiting spatial locality in data caches using spatial footprints
inferredcites →https://doi.org/10.1145/301618.301633openalex-snapshot
Cache-conscious structure layout
inferredcites →https://doi.org/10.1145/305138.305156openalex-snapshot
The pool of subsectors cache design
inferredcites →https://doi.org/10.1145/305138.305188openalex-snapshot
Adapting cache line size to application behavior
inferredcites →https://doi.org/10.1145/339647.339669openalex-snapshot
Selective, accurate, and timely self-invalidation using last-touch prediction
inferredcites →https://doi.org/10.1145/545214.545239openalex-snapshot
Timekeeping in the memory system
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/s11227-017-2144-1openalex-snapshot
A performance study of the time-varying cache behavior: a study on APEX, Mantevo, NAS, and PARSEC
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Irregular accesses reorder unit: improving GPGPU memory coalescing for graph-based workloads
inferred← citeshttps://doi.org/10.1007/s11390-014-1429-6openalex-snapshot
Reinventing Memory System Design for Many-Accelerator Architecture
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P3DC: Reducing DRAM Cache Hit Latency by Hybrid Mappings
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Optimization strategies for GPUs: an overview of architectural approaches
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BoDNoC: Providing bandwidth-on-demand interconnection for multi-granularity memory systems
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Cache Utilization as a Locality Metric - A Case Study on the Mantevo Suite
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Dalorex: A Data-Local Program Execution and Architecture for Memory-bound Applications
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Piccolo: Large-Scale Graph Processing with Fine-Grained in-Memory Scatter-Gather
inferred← citeshttps://doi.org/10.1109/hpcc/smartcity/dss.2019.00064openalex-snapshot
Characterizations and Architectural Implications of NVM's External DRAM Cache
inferred← citeshttps://doi.org/10.1109/icccs55155.2022.9846314openalex-snapshot
STAFF: A Model for Structure Layout Optimization
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Increasing cache capacity via critical-words-only cache
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Data placement across the cache hierarchy: Minimizing data movement with reuse-aware placement
inferred← citeshttps://doi.org/10.1109/iccd.2017.62openalex-snapshot
Jenga: Efficient Fault Tolerance for Stacked DRAM
inferred← citeshttps://doi.org/10.1109/iccd58817.2023.00029openalex-snapshot
Morpheus: An Adaptive DRAM Cache with Online Granularity Adjustment for Disaggregated Memory
inferred← citeshttps://doi.org/10.1109/iiswc.2016.7581276openalex-snapshot
ID-cache: instruction and memory divergence based cache management for GPUs
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The Implications of Page Size Management on Graph Analytics
inferred← citeshttps://doi.org/10.1109/ipdps.2017.81openalex-snapshot
Elastic-Cache: GPU Cache Architecture for Efficient Fine- and Coarse-Grained Cache-Line Management
inferred← citeshttps://doi.org/10.1109/isca66397.2026.00057openalex-snapshot
SMOOTH: Hardware-Assisted Fine-Grained On-Chip Memory Management for Efficient On-Device LLM Inference
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Eliminating on-chip traffic waste: are we there yet?
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Performance and energy evaluation of data prefetching on intel Xeon Phi
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An Application-Tailored Approach to Hardware Cache Coherence
inferred← citeshttps://doi.org/10.1109/micro.2014.36openalex-snapshot
Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and Bandwidth
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BuMP: Bulk Memory Access Prediction and Streaming
inferred← citeshttps://doi.org/10.1109/micro.2014.51openalex-snapshot
Unison Cache: A Scalable and Effective Die-Stacked DRAM Cache
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Rethinking the Memory Hierarchy for Modern Languages
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Weeding out Front-End Stalls with Uneven Block Size Instruction Cache
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LMStr: Local memory store the case for hardware controlled scratchpad memory for general purpose processors
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Practical Temporal Prefetching With Compressed On-Chip Metadata
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Cacheline Utilization-Aware Link Traffic Compression for Modular GPUs
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Structure layout optimization based on GCC
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Die-stacked DRAM caches for servers
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Die-stacked DRAM caches for servers
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Data Criticality in Network-On-Chip Design
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Inefficiencies in the Cache Hierarchy
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