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BuMP: Bulk Memory Access Prediction and Streaming
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1088/1748-9326/3/3/034008openalex-snapshot
Worldwide electricity used in data centers
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Improving CC-NUMA performance using Instruction-based Prediction
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Reducing DRAM latencies with an integrated memory hierarchy design
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Accurate and Complexity-Effective Spatial Pattern Prediction
inferredcites →https://doi.org/10.1109/hpca.2010.5416628openalex-snapshot
An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth
inferredcites →https://doi.org/10.1109/hpca.2012.6168944openalex-snapshot
Balancing DRAM locality and parallelism in shared memory CMP systems
inferredcites →https://doi.org/10.1109/iccad.2011.6105405openalex-snapshot
CACTI-P: Architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques
inferredcites →https://doi.org/10.1109/iedm.2005.1609253openalex-snapshot
Scaling, power, and the future of CMOS
inferredcites →https://doi.org/10.1109/iiswc.2008.4636095openalex-snapshot
Temporal streams in commercial server applications
inferredcites →https://doi.org/10.1109/isca.1998.694794openalex-snapshot
Exploiting spatial locality in data caches using spatial footprints
inferredcites →https://doi.org/10.1109/isca.2012.6237027openalex-snapshot
Improving writeback efficiency with decoupled last-write prediction
inferredcites →https://doi.org/10.1109/isca.2012.6237047openalex-snapshot
The dynamic granularity memory system
inferredcites →https://doi.org/10.1109/isscc.2012.6176878openalex-snapshot
The next-generation 64b SPARC core in a T4 SoC processor
inferredcites →https://doi.org/10.1109/jssc.2012.2223036openalex-snapshot
The Next Generation 64b SPARC Core in a T4 SoC Processor
inferredcites →https://doi.org/10.1109/l-ca.2008.13openalex-snapshot
Multicore DIMM: an Energy Efficient Memory Module with Independently Controlled DRAMs
inferredcites →https://doi.org/10.1109/l-ca.2011.4openalex-snapshot
DRAMSim2: A Cycle Accurate Memory System Simulator
inferredcites →https://doi.org/10.1109/micro.2007.30openalex-snapshot
Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow
inferredcites →https://doi.org/10.1109/micro.2007.33openalex-snapshot
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0
inferredcites →https://doi.org/10.1109/micro.2008.4771792openalex-snapshot
Mini-rank: Adaptive DRAM architecture for improving memory power efficiency
inferredcites →https://doi.org/10.1109/micro.2010.51openalex-snapshot
Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior
inferredcites →https://doi.org/10.1109/micro.2012.42openalex-snapshot
Amoeba-Cache: Adaptive Blocks for Eliminating Waste in the Memory Hierarchy
inferredcites →https://doi.org/10.1109/mm.2006.79openalex-snapshot
SimFlex: Statistical Sampling of Computer System Simulation
inferredcites →https://doi.org/10.1109/mm.2012.71openalex-snapshot
Optimizing Data-Center TCO with Scale-Out Processors
inferredcites →https://doi.org/10.1109/mm.2014.41openalex-snapshot
A Case for Specialized Processors for Scale-Out Workloads
inferredcites →https://doi.org/10.1109/nocs.2012.15openalex-snapshot
CCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache-Coherent Servers
inferredcites →https://doi.org/10.1145/1815961.1815983openalex-snapshot
Rethinking DRAM design and organization for energy-constrained multi-cores
inferredcites →https://doi.org/10.1145/1998582.1998590openalex-snapshot
Memory power management via dynamic voltage/frequency scaling
inferredcites →https://doi.org/10.1145/1999946.1999983openalex-snapshot
Reducing Network-on-Chip energy consumption through spatial locality speculation
inferredcites →https://doi.org/10.1145/2000064.2000108openalex-snapshot
Dark silicon and the end of multicore scaling
inferredcites →https://doi.org/10.1145/2366231.2337164openalex-snapshot
Towards energy-proportional datacenter memory with mobile DRAM
inferredcites →https://doi.org/10.1145/2366231.2337195openalex-snapshot
Improving writeback efficiency with decoupled last-write prediction
inferredcites →https://doi.org/10.1145/2366231.2337222openalex-snapshot
The dynamic granularity memory system
inferredcites →https://doi.org/10.1145/2485922.2485957openalex-snapshot
Die-stacked DRAM caches for servers
inferredcites →https://doi.org/10.1145/279358.279404openalex-snapshot
Exploiting spatial locality in data caches using spatial footprints
inferredcites →https://doi.org/10.1145/360128.360132openalex-snapshot
Eager writeback - a technique for improving bandwidth utilization
inferredcites →https://doi.org/10.1184/r1/6468701openalex-snapshot
DRAM-Aware Last-Level Cache Writeback: Reducing Write-Caused Interference in Memory Systems
inferredcites →https://doi.org/10.2200/s00193ed1v01y200905cac006openalex-snapshot
The Datacenter as a Computer: An Introduction to the Design of Warehouse-Scale Machines
inferredcites →https://doi.org/10.2200/s00516ed2v01y201306cac024openalex-snapshot
The Datacenter as a Computer: An Introduction to the Design of Warehouse-Scale Machines, Second edition
inferredcites →https://doi.org/10.5555/2132325.2132479openalex-snapshot
CACTI-P: architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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Asymmetrical topology and entropy-based heterogeneous link for many-core massive data communication
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Supporting faulty banks in NUCA by NoC assisted remapping mechanisms
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Building Emulation Framework for Non-Volatile Memory
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Fusion: A Data Prefetcher Synergizing Instruction Information and Spatial Patterns
inferred← citeshttps://doi.org/10.1109/hpca.2016.7446068openalex-snapshot
Efficient footprint caching for Tagless DRAM Caches
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Predicting the memory bandwidth and optimal core allocations for multi-threaded applications on large-scale NUMA machines
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MemPod: A Clustered Architecture for Efficient and Scalable Migration in Flat Address Space Multi-level Memories
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PageSeer: Using Page Walks to Trigger Page Swaps in Hybrid Memory Systems
inferred← citeshttps://doi.org/10.1109/hpca.2019.00053openalex-snapshot
Bingo Spatial Data Prefetcher
inferred← citeshttps://doi.org/10.1109/hpca61900.2025.00024openalex-snapshot
Gaze into the Pattern: Characterizing Spatial Patterns with Internal Temporal Correlations for Hardware Prefetching
inferred← citeshttps://doi.org/10.1109/isca.2018.00027openalex-snapshot
A Case for Richer Cross-Layer Abstractions: Bridging the Semantic Gap with Expressive Memory
inferred← citeshttps://doi.org/10.1109/micro.2014.51openalex-snapshot
Unison Cache: A Scalable and Effective Die-Stacked DRAM Cache
inferred← citeshttps://doi.org/10.1109/micro.2018.00036openalex-snapshot
Neighborhood-Aware Address Translation for Irregular GPU Applications
inferred← citeshttps://doi.org/10.1109/micro.2018.00052openalex-snapshot
Farewell My Shared LLC! A Case for Private Die-Stacked DRAM Caches for Servers
inferred← citeshttps://doi.org/10.1109/micro56248.2022.00070openalex-snapshot
Page Size Aware Cache Prefetching
inferred← citeshttps://doi.org/10.1109/mwent47943.2020.9067412openalex-snapshot
Increasing DDR4 SDRAM throughput in parallel workloads
inferred← citeshttps://doi.org/10.1109/pact52795.2021.00024openalex-snapshot
Invalidate or Update? Revisiting Coherence for Tomorrow's Cache Hierarchies
inferred← citeshttps://doi.org/10.1109/tcad.2024.3442981openalex-snapshot
PARS: A Pattern-Aware Spatial Data Prefetcher Supporting Multiple Region Sizes
inferred← citeshttps://doi.org/10.1109/tpds.2017.2763141openalex-snapshot
Alleviating Memory Refresh Overhead via Data Compression for High Performance and Energy Efficiency
inferred← citeshttps://doi.org/10.1109/tvlsi.2015.2420315openalex-snapshot
Low-Power Hybrid Memory Cubes With Link Power Management and Two-Level Prefetching
inferred← citeshttps://doi.org/10.1145/3240302.3240310openalex-snapshot
Design guidelines for high-performance SCM hierarchies
inferred← citeshttps://doi.org/10.1145/3240302.3240315openalex-snapshot
A performance & power comparison of modern high-speed DRAM architectures
inferred← citeshttps://doi.org/10.1145/3273982.3273992openalex-snapshot
Algorithm/Architecture Co-Design for Near-Memory Processing
inferred← citeshttps://doi.org/10.1145/3565885openalex-snapshot
FlexHM: A Practical System for Heterogeneous Memory with Flexible and Efficient Performance Optimizations
inferred← citeshttps://doi.org/10.1145/3658644.3690183openalex-snapshot
Principled Microarchitectural Isolation on Cloud CPUs
inferred← citeshttps://doi.org/10.1587/transele.e101.c.170openalex-snapshot
Energy-Efficient DRAM Selective Refresh Technique with Page Residence in a Memory Hierarchy of Hardware-Managed TLB
inferred← citeshttps://doi.org/10.21203/rs.3.rs-3853411/v1openalex-snapshot
DMDP: A Dynamic Multi-Delta Prefetcher with Customizable Runtime Quality-Aware Feedback
inferred← citeshttps://doi.org/10.3850/9783981537079_0980openalex-snapshot
Towards Near-Threshold Server Processors
inferred← citeshttps://doi.org/10.48550/arxiv.1612.00445openalex-snapshot
Near-Memory Address Translation
inferred← citeshttps://doi.org/10.5075/epfl-thesis-6631openalex-snapshot
Multi-Gigabyte On-Chip DRAM Caches for Servers
inferred← citeshttps://doi.org/10.5821/dissertation-2117-403959openalex-snapshot
Advanced hardware prefetching in virtual memory systems
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