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Arbitrary Modulus Indexing
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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1002/0471648299.ch7openalex-snapshot
Performance Analysis and Optimization
inferredcites →https://doi.org/10.1109/12.754999openalex-snapshot
A comparative analysis of cache designs for vector processing
inferredcites →https://doi.org/10.1109/2.889095openalex-snapshot
Making pointer-based data structures cache conscious
inferredcites →https://doi.org/10.1109/40.621212openalex-snapshot
Two fast and high-associativity cache schemes
inferredcites →https://doi.org/10.1109/hpca.2004.10015openalex-snapshot
Using Prime Numbers for Cache Indexing to Eliminate Conflict Misses
inferredcites →https://doi.org/10.1109/hpca.2011.5749726openalex-snapshot
Cuckoo directory: A scalable directory for many-core systems
inferredcites →https://doi.org/10.1109/iccad.2004.1382556openalex-snapshot
Reducing cache misses by application-specific re-configurable indexing
inferredcites →https://doi.org/10.1109/iiswc.2009.5306797openalex-snapshot
Rodinia: A benchmark suite for heterogeneous computing
inferredcites →https://doi.org/10.1109/isca.1993.698558openalex-snapshot
Acase For Two-way Skewed-associative Caches
inferredcites →https://doi.org/10.1109/ispass.2009.4919648openalex-snapshot
Analyzing CUDA workloads using a detailed GPU simulator
inferredcites →https://doi.org/10.1109/ispass.2010.5452013openalex-snapshot
Demystifying GPU microarchitecture through microbenchmarking
inferredcites →https://doi.org/10.1109/micro.2010.20openalex-snapshot
The ZCache: Decoupling Ways and Associativity
inferredcites →https://doi.org/10.1109/tc.1982.1676020openalex-snapshot
The Prime Memory System for Array Access
inferredcites →https://doi.org/10.1109/tc.1983.1676162openalex-snapshot
Comments on "The Prime Memory Systems for Array Access"
inferredcites →https://doi.org/10.1109/tc.2005.79openalex-snapshot
Eliminating Conflict Misses Using Prime Number-Based Cache Indexing
inferredcites →https://doi.org/10.1145/115952.115961openalex-snapshot
Pseudo-randomly interleaved memory
inferredcites →https://doi.org/10.1145/115953.115961openalex-snapshot
Pseudo-randomly interleaved memory
inferredcites →https://doi.org/10.1145/125826.125874openalex-snapshot
A ultra fast Euclidean division algorithm for prime memory systems
inferredcites →https://doi.org/10.1145/139669.140398openalex-snapshot
A novel cache design for vector processing
inferredcites →https://doi.org/10.1145/143369.143403openalex-snapshot
Conflict-free access of vectors with power-of-two strides
inferredcites →https://doi.org/10.1145/165123.165152openalex-snapshot
A case for two-way skewed-associative caches
inferredcites →https://doi.org/10.1145/165123.165172openalex-snapshot
The Chinese remainder theorem and the prime memory system
inferredcites →https://doi.org/10.1145/165123.165175openalex-snapshot
Odd memory systems may be quite interesting
inferredcites →https://doi.org/10.1145/173682.165175openalex-snapshot
Odd memory systems may be quite interesting
inferredcites →https://doi.org/10.1145/195470.195527openalex-snapshot
Avoiding conflict misses dynamically in large direct-mapped caches
inferredcites →https://doi.org/10.1145/195473.195527openalex-snapshot
Avoiding conflict misses dynamically in large direct-mapped caches
inferredcites →https://doi.org/10.1145/2000064.2000093openalex-snapshot
Energy-efficient mechanisms for managing thread context in throughput processors
inferredcites →https://doi.org/10.1145/223982.224447openalex-snapshot
Streamlining data cache access with fast address calculation
inferredcites →https://doi.org/10.1145/2485922.2485951openalex-snapshot
Orchestrated scheduling and prefetching for GPGPUs
inferredcites →https://doi.org/10.1145/339647.339660openalex-snapshot
A fully associative software-managed cache design
inferredcites →https://doi.org/10.1145/775832.776052openalex-snapshot
Improved indexing for cache miss reduction in embedded systems
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1002/9781119818298.ch8openalex-snapshot
Study and Comparison of Hardware Methods for Distributing Memory Bank Accesses in Many‐core Architectures
inferred← citeshttps://doi.org/10.1007/978-3-030-49345-5_28openalex-snapshot
Optimization of Application-Specific L1 Cache Translation Functions of the LEON3 Processor
inferred← citeshttps://doi.org/10.1016/j.jpdc.2018.11.012openalex-snapshot
A survey of architectural approaches for improving GPGPU performance, programmability and heterogeneity
inferred← citeshttps://doi.org/10.1016/j.micpro.2016.01.003openalex-snapshot
Quantifying the performance and energy efficiency of advanced cache indexing for GPGPU computing
inferred← citeshttps://doi.org/10.1109/candar.2015.94openalex-snapshot
A Challenge for an Efficient AMI-based Cache System on FPGA Soft Processors
inferred← citeshttps://doi.org/10.1109/candarw51189.2020.00085openalex-snapshot
A Conflict-Aware Capacity Control Mechanism for Last-Level Cache
inferred← citeshttps://doi.org/10.1109/dsn.2018.00041openalex-snapshot
Low Overhead Tag Error Mitigation for GPU Architectures
inferred← citeshttps://doi.org/10.1109/fpt.2017.8280144openalex-snapshot
Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor
inferred← citeshttps://doi.org/10.1109/hpec58863.2023.10363536openalex-snapshot
In-Place Multicore SIMD Fast Fourier Transforms
inferred← citeshttps://doi.org/10.1109/iccd.2016.7753308openalex-snapshot
IACM: Integrated adaptive cache management for high-performance and energy-efficient GPGPU computing
inferred← citeshttps://doi.org/10.1109/micro61859.2024.00041openalex-snapshot
Customizing Cache Indexing Through Entropy Estimation
inferred← citeshttps://doi.org/10.1109/tc.2015.2479595openalex-snapshot
Configurable XOR Hash Functions for Banked Scratchpad Memories in GPUs
inferred← citeshttps://doi.org/10.1109/tpds.2017.2657512openalex-snapshot
Dynamic Associativity Management in Tiled CMPs by Runtime Adaptation of Fellow Sets
inferred← citeshttps://doi.org/10.1109/tpds.2018.2868658openalex-snapshot
Improving the Performance and Energy Efficiency of GPGPU Computing through Integrated Adaptive Cache Management
inferred← citeshttps://doi.org/10.1145/2768177.2768179openalex-snapshot
On the Feasibility of Advanced Cache Indexing for High-Performance and Energy-Efficient GPGPU Computing
inferred← citeshttps://doi.org/10.1145/2811402openalex-snapshot
Spatiotemporal SIMT and Scalarization for Improving GPU Efficiency
inferred← citeshttps://doi.org/10.1145/3721145.3729513openalex-snapshot
A Cost-Effective Dueling Framework for Set-Associative Cache Indexing
inferred← citeshttps://doi.org/10.1587/transinf.2016edp7414openalex-snapshot
Skewed Multistaged Multibanked Register File for Area and Energy Efficiency
inferred← citeshttps://doi.org/10.1587/transinf.2021edp7201openalex-snapshot
A Conflict-Aware Capacity Control Mechanism for Deep Cache Hierarchy
inferred← citeshttps://doi.org/10.3233/his-200281openalex-snapshot
Evolution of application-specific cache mappings
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