On the public citation graph
(FPL 2015) Scavenger
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Inferred edges come from two machine sources: sweeps of open repository metadata (mostly SSRN and Zenodo), and a bulk OpenAlex citation snapshot. Every row below is labelled with the one it came from. Neither is a complete citation index — absence here is not evidence of absence.
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-319-26408-0_14openalex-snapshot
The LEAP FPGA Operating System
inferredcites →https://doi.org/10.1109/.9openalex-snapshot
Analysis of TCP and DTN Retransmission Algorithms in Presence of Channel Disruptions
inferredcites →https://doi.org/10.1109/date.2011.5763218openalex-snapshot
MARC II: A parametrized speculative multi-ported memory subsystem for reconfigurable computers
inferredcites →https://doi.org/10.1109/fccm.2010.28openalex-snapshot
Designing Modular Hardware Accelerators in C with ROCCC 2.0
inferredcites →https://doi.org/10.1109/fccm.2012.13openalex-snapshot
Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems
inferredcites →https://doi.org/10.1109/fccm.2014.43openalex-snapshot
LEAP Shared Memories: Automating the Construction of FPGA Coherent Memories
inferredcites →https://doi.org/10.1109/fpl.2012.6339185openalex-snapshot
Polyblaze: From one to many bringing the microblaze into the multicore era with Linux SMP support
inferredcites →https://doi.org/10.1109/fpl.2014.6927471openalex-snapshot
Adaptive Dynamic On-chip Memory Management for FPGA-based reconfigurable architectures
inferredcites →https://doi.org/10.1109/fpl.2014.6927488openalex-snapshot
The LEAP FPGA operating system
inferredcites →https://doi.org/10.1109/fpl.2015.7294018openalex-snapshot
Scavenger: Automating the construction of application-optimized memory hierarchies
inferredcites →https://doi.org/10.1109/hpca.2011.5749747openalex-snapshot
HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing
inferredcites →https://doi.org/10.1109/reconfig.2011.8openalex-snapshot
Adaptive Multi-client Network-on-Chip Memory
inferredcites →https://doi.org/10.1109/tc.1982.1676020openalex-snapshot
The Prime Memory System for Array Access
inferredcites →https://doi.org/10.1109/tcad.2011.2110592openalex-snapshot
High-Level Synthesis for FPGAs: From Prototyping to Deployment
inferredcites →https://doi.org/10.1109/tpami.2002.1017616openalex-snapshot
An efficient k-means clustering algorithm: analysis and implementation
inferredcites →https://doi.org/10.1145/165123.165172openalex-snapshot
The Chinese remainder theorem and the prime memory system
inferredcites →https://doi.org/10.1145/1723112.1723122openalex-snapshot
Efficient multi-ported memories for FPGAs
inferredcites →https://doi.org/10.1145/2684746.2689083openalex-snapshot
Design Space Exploration of L1 Data Caches for FPGA-Based Multiprocessor Systems
inferredcites →https://doi.org/10.1145/605397.605420openalex-snapshot
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
inferredcites →https://doi.org/10.5555/789083.1022819openalex-snapshot
Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
inferred← citeshttps://doi.org/10.1007/978-3-030-20721-2_3openalex-snapshot
Hardware Accelerators for Data Search
inferred← citeshttps://doi.org/10.1007/978-3-030-20721-2_6openalex-snapshot
Hardware/Software Co-design
inferred← citeshttps://doi.org/10.1007/978-3-319-53222-6_5openalex-snapshot
Custom Multi-cache Architectures
inferred← citeshttps://doi.org/10.1016/j.sysarc.2021.101991openalex-snapshot
SparkNoC: An energy-efficiency FPGA-based accelerator using optimized lightweight CNN for edge computing
inferred← citeshttps://doi.org/10.1016/j.vlsi.2021.02.004openalex-snapshot
Designing efficient FPGA tiles for power-constrained ultra-low-power applications
inferred← citeshttps://doi.org/10.1109/fpt.2015.7393141openalex-snapshot
Custom-sized caches in application-specific memory hierarchies
inferred← citeshttps://doi.org/10.1109/iccd.2016.7753312openalex-snapshot
Scalable memory architecture for soft-core processors
inferred← citeshttps://doi.org/10.1109/tcad.2016.2608861openalex-snapshot
Custom Multicache Architectures for Heap Manipulating Programs
inferred← citeshttps://doi.org/10.1145/3020078.3021748openalex-snapshot
Automatic Construction of Program-Optimized FPGA Memory Networks
inferred← citeshttps://doi.org/10.23919/date.2019.8715190openalex-snapshot
Automatic data placement for CPU-FPGA heterogeneous multiprocessor System-on-Chips
inferred← citeshttps://doi.org/10.7916/d8-4yxc-gz97openalex-snapshot
Compiling Irregular Software to Specialized Hardware
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