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Iso-X: A Flexible Architecture for Hardware-Managed Isolated Execution
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What this work says
Outgoing claims: the papers this work cites, builds on, or argues with.
inferredcites →https://doi.org/10.1007/978-3-540-87403-4_1openalex-snapshot
Guest-Transparent Prevention of Kernel Rootkits with VMM-Based Memory Shadowing
inferredcites →https://doi.org/10.1109/ccst.2002.1049236openalex-snapshot
Improving security in information technology using cryptographic hardware modules
inferredcites →https://doi.org/10.1109/hpca.2010.5416657openalex-snapshot
Scalable architectural support for trusted software
inferredcites →https://doi.org/10.1109/hpca.2013.6522323openalex-snapshot
Architecture support for guest-transparent VM protection from untrusted hypervisor and physical attacks
inferredcites →https://doi.org/10.1109/hpca.2014.6835931openalex-snapshot
A Non-Inclusive Memory Permissions architecture for protection against cross-layer attacks
inferredcites →https://doi.org/10.1109/micro.2003.1253207openalex-snapshot
Efficient memory integrity verification and encryption for secure processors
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A novel cache architecture with enhanced performance and security
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CSI Kernel: Finding a Needle in a Multiterabyte Haystack
inferredcites →https://doi.org/10.1109/sp.2012.42openalex-snapshot
Building Verifiable Trusted Path on Commodity x86 Computers
inferredcites →https://doi.org/10.1109/sp.2013.24openalex-snapshot
PrivExec: Private Execution as an Operating System Service
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A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-μm CMOS technology
inferredcites →https://doi.org/10.1145/1080695.1069971openalex-snapshot
Architecture for Protecting Critical Secrets in Microprocessors
inferredcites →https://doi.org/10.1145/1080695.1069974openalex-snapshot
Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions
inferredcites →https://doi.org/10.1145/1315245.1315294openalex-snapshot
Hardware-rooted trust for secure key management and transient trust
inferredcites →https://doi.org/10.1145/2133352.2133354openalex-snapshot
On the exploitation of a high-throughput SHA-256 FPGA design for HMAC
inferredcites →https://doi.org/10.1145/2150976.2151022openalex-snapshot
Architectural support for hypervisor-secure virtualization
inferredcites →https://doi.org/10.1145/2155620.2155652openalex-snapshot
Architectural support for secure virtualization under a vulnerable hypervisor
inferredcites →https://doi.org/10.1145/2484402.2484406openalex-snapshot
Characterizing hypervisor vulnerabilities in cloud computing servers
inferredcites →https://doi.org/10.1145/2487726.2488368openalex-snapshot
Innovative instructions and software model for isolated execution
inferredcites →https://doi.org/10.1145/2487726.2488370openalex-snapshot
Using innovative instructions to create trustworthy software solutions
inferredcites →https://doi.org/10.1145/359460.359473openalex-snapshot
Secure communications over insecure channels
inferredcites →https://doi.org/10.1145/378995.379237openalex-snapshot
Architectural support for copy and tamper resistant software
inferredcites →https://doi.org/10.1145/384264.379237openalex-snapshot
Architectural support for copy and tamper resistant software
inferredcites →https://doi.org/10.5555/1251229.1251252openalex-snapshot
Processes in KaffeOS: isolation, resource management, and sharing in java
inferredcites →https://doi.org/10.5555/956417.956575openalex-snapshot
Efficient memory integrity verification and encryption for secure processors
What points at this work
Incoming claims: where this work appears in other papers’ reference lists and arguments.
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HyperTEE: A Decoupled TEE Architecture with Secure Enclave Management
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SoK: Limitations of Confidential Computing via TEEs for High-Performance Compute Systems
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CaSE: Cache-Assisted Secure Execution on ARM Processors
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Hardware-Based Malware Detection Using Low-Level Architectural Features
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Hardware-Based Trusted Computing Architectures for Isolation and Attestation
inferred← citeshttps://doi.org/10.1109/tc.2020.2996021openalex-snapshot
OPTIMUS: A Security-Centric Dynamic Hardware Partitioning Scheme for Processors that Prevent Microarchitecture State Attacks
inferred← citeshttps://doi.org/10.1109/tcc.2015.2511730openalex-snapshot
CypherDB: A Novel Architecture for Outsourcing Secure Database Processing
inferred← citeshttps://doi.org/10.1109/tdsc.2016.2596287openalex-snapshot
Flexible Hardware-Managed Isolated Execution: Architecture, Software Support and Applications
inferred← citeshttps://doi.org/10.1109/tdsc.2022.3147262openalex-snapshot
ShieLD: Shielding Cross-Zone Communication Within Limited-Resourced IoT Devices Running Vulnerable Software Stack
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Surviving Information Leakage Hardware Trojan Attacks Using Hardware Isolation
inferred← citeshttps://doi.org/10.1109/trustcom.2016.0293openalex-snapshot
SecPage - A Lightweight Memory Protection Architecture
inferred← citeshttps://doi.org/10.1145/2768566.2768571openalex-snapshot
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inferred← citeshttps://doi.org/10.1145/2842621openalex-snapshot
Rethinking Memory Permissions for Protection Against Cross-Layer Attacks
inferred← citeshttps://doi.org/10.1145/2870636openalex-snapshot
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Covert Channels through Random Number Generator
inferred← citeshttps://doi.org/10.1145/3037697.3037739openalex-snapshot
Verification of a Practical Hardware Security Architecture Through Static Information Flow Analysis
inferred← citeshttps://doi.org/10.1145/3052973.3052999openalex-snapshot
On the Detection of Kernel-Level Rootkits Using Hardware Performance Counters
inferred← citeshttps://doi.org/10.1145/3093315.3037739openalex-snapshot
Verification of a Practical Hardware Security Architecture Through Static Information Flow Analysis
inferred← citeshttps://doi.org/10.1145/3093336.3037739openalex-snapshot
Verification of a Practical Hardware Security Architecture Through Static Information Flow Analysis
inferred← citeshttps://doi.org/10.1145/3093337.3037739openalex-snapshot
Verification of a Practical Hardware Security Architecture Through Static Information Flow Analysis
inferred← citeshttps://doi.org/10.1145/3287306openalex-snapshot
An Exhaustive Survey on Security Concerns and Solutions at Different Components of Virtualization
inferred← citeshttps://doi.org/10.1145/3411505.3418437openalex-snapshot
Protecting Enclaves from Intra-Core Side-Channel Attacks through Physical Isolation
inferred← citeshttps://doi.org/10.1145/3503222.3507733openalex-snapshot
ShEF: shielded enclaves for cloud FPGAs
inferred← citeshttps://doi.org/10.1145/3627703.3650071openalex-snapshot
SmartNIC Security Isolation in the Cloud with S-NIC
inferred← citeshttps://doi.org/10.1145/3640537.3641564openalex-snapshot
Compiler-Based Memory Encryption for Machine Learning on Commodity Low-Power Devices
inferred← citeshttps://doi.org/10.1145/3649329.3658241openalex-snapshot
SecPaging: Secure Enclave Paging with Hardware-Enforced Protection against Controlled-Channel Attacks
inferred← citeshttps://doi.org/10.1145/3672392openalex-snapshot
A Survey of Hardware Improvements to Secure Program Execution
inferred← citeshttps://doi.org/10.1145/3715014.3722057openalex-snapshot
TOCTOU Resilient Attestation for IoT Networks
inferred← citeshttps://doi.org/10.1145/3844614openalex-snapshot
Lattice: Enabling Scalable Enclaves for Commercial RISC-V Platforms
inferred← citeshttps://doi.org/10.14722/ndss.2019.23068openalex-snapshot
TIMBER-V: Tag-Isolated Memory Bringing Fine-grained Enclaves to RISC-V
inferred← citeshttps://doi.org/10.22456/2175-2745.77654openalex-snapshot
Avaliação do Intel Software Guard Extensions via Emulação
inferred← citeshttps://doi.org/10.48456/tr-887openalex-snapshot
Hardware support for compartmentalisation
inferred← citeshttps://doi.org/10.48550/arxiv.1712.08519openalex-snapshot
The Heisenberg Defense: Proactively Defending SGX Enclaves against Page-Table-Based Side-Channel Attacks
inferred← citeshttps://doi.org/10.48550/arxiv.1803.03951openalex-snapshot
The Secure Machine: Efficient Secure Execution On Untrusted Platforms
inferred← citeshttps://doi.org/10.48550/arxiv.1812.09822openalex-snapshot
MI6: Secure Enclaves in a Speculative Out-of-Order Processor
inferred← citeshttps://doi.org/10.48550/arxiv.1907.10119openalex-snapshot
Keystone: An Open Framework for Architecting TEEs
inferred← citeshttps://doi.org/10.5555/3195638.3195684openalex-snapshot
Poisonivy: safe speculation for secure memory
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Hardening extended memory access control schemes with self-verified address spaces
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Graviton: trusted execution environments on GPUs
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An In-Depth Study and Implementation of Protection Mechanisms For Embedded Devices Running Multiple Applications
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